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  • c8847b27e8 all conversions go through the execute stage result mux Katherine Parry 2021-08-16 13:06:09 -0400
  • a70d51f4c9 Modified the hptw's simulation error message so that synthesis does not attempt to include this statement. Ross Thompson 2021-08-16 10:02:29 -0500
  • 36761d9155 Fixed syntax errors in some floating point modules. This came up in Xilinx synthesis. Ross Thompson 2021-08-15 16:48:49 -0500
  • 6c57002d0e Added logic to linux test bench to not stop simulation on csr write faults. Ross Thompson 2021-08-15 11:13:32 -0500
  • af2c6fd6ff Updated linux-wave.do to have cursors at the timer interrupt problem. Ross Thompson 2021-08-13 17:29:37 -0500
  • 766c829d31 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-08-13 17:23:04 -0500
  • 55fda4de62 Switched ExceptionM to dcache to be just exceptions. Added test bench logic to hold forces until the W stage is unstalled. Ross Thompson 2021-08-13 15:53:24 -0500
  • 32db21659f Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token. Ross Thompson 2021-08-13 14:53:43 -0500
  • e141a00934 Cleaned up the linux testbench by removing old code and signals. Added back in the csr checking logic. Added code to force timer, external, and software interrupts by using the expected values from qemu's (m/s)cause registers. Still need to prevent wally's timer interrupt. Ross Thompson 2021-08-13 14:39:05 -0500
  • aedd71d570 move some FPU select muxs to execute stage Katherine Parry 2021-08-13 14:41:22 -0400
  • 4f5007a9ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-08-12 18:05:48 -0500
  • 6a6d5e9b15 Added documentation about how the dcache and ptw interact. Ross Thompson 2021-08-12 18:05:36 -0500
  • 814fd80b0f Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate. Ross Thompson 2021-08-12 13:36:33 -0500
  • 9ff9c4dff9 Minor cleanup of the linux test bench. Ross Thompson 2021-08-12 11:14:55 -0500
  • 44c7494a30 Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. Abe 2021-08-12 05:23:04 -0400
  • 565c01709d Removed unused states from dcache fsm. Ross Thompson 2021-08-11 17:06:09 -0500
  • 2be625d8b9 Modified invalid plic reads to return 0 rather than deadbeaf. Ross Thompson 2021-08-11 16:56:22 -0500
  • 4b25fed6d8 Simplified Dcache by sharing the read data mux with the victim selection mux. Ross Thompson 2021-08-11 16:55:55 -0500
  • 22f274c51e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-08-10 13:36:29 -0500
  • 67c1028862 Dcache and LSU clean up. Ross Thompson 2021-08-10 13:36:21 -0500
  • e00f181bcf LZA added to FMA and attemting a merged FMA and adder in synthesis Katherine Parry 2021-08-10 13:57:16 -0400
  • cce0571925 Fixed another bug with the atomic instrucitons implemention in the dcache. Ross Thompson 2021-08-08 22:50:31 -0500
  • d3be04b7de Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled providing the new update dated rather than the correct older value. Ross Thompson 2021-08-08 11:42:10 -0500
  • fc7016eea6 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. Fixed logic for trace update in the M and W stages. The M stage should not update if there is an instruction fault. Ross Thompson 2021-08-08 00:28:18 -0500
  • aa9a5d879b Finally past the CLINT issues. Ross Thompson 2021-08-06 16:41:34 -0500
  • 0bfbcef8ab Now past the CLINT issues. Ross Thompson 2021-08-06 16:16:39 -0500
  • 9be10cdc8b Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts. Ross Thompson 2021-08-06 16:06:50 -0500
  • c749d08542 fixed the read timer issue but we still have problems with interrupts and i/o devices. Ross Thompson 2021-08-06 10:16:06 -0500
  • 3582be4dbb Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction. Ross Thompson 2021-08-05 16:49:03 -0500
  • 37ba6b19e5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-30 17:57:13 -0500
  • f808b29065 Added some comments to linux testbench. Ross Thompson 2021-07-30 17:57:03 -0500
  • e166cc84ee Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files. Ross Thompson 2021-07-30 14:24:50 -0500
  • 74fba4bb06 Moved the test bench modules to a common directory. Ross Thompson 2021-07-30 14:16:14 -0500
  • 7b9e53fbe5 Removed 1 cycle delay on store miss. Changed some logic to partially support atomics. Ross Thompson 2021-07-30 14:00:51 -0500
  • d8878581f4 Created new linux test bench and parsing scripts. Ross Thompson 2021-07-29 20:26:50 -0500
  • d60e394ef9 all fpu units use the unpacking unit Katherine Parry 2021-07-28 23:49:21 -0400
  • 915d8136e5 Fixed bug which caused stores to take an extra clock cycle. Ross Thompson 2021-07-26 12:22:53 -0500
  • 79ebc53977 Fixed bug with the compressed immediate generation. Several formats should zero extend. Ross Thompson 2021-07-26 11:55:31 -0500
  • ef55b30e99 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-26 11:55:00 -0500
  • 60177b92a6 Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation. Ross Thompson 2021-07-25 23:14:28 -0500
  • 30ac22edff fixed some fpu lint errors Katherine Parry 2021-07-24 16:41:12 -0400
  • 6c4aa624a5 fpu cleanup Katherine Parry 2021-07-24 15:00:56 -0400
  • ef28679721 fpu cleanup Katherine Parry 2021-07-24 14:59:57 -0400
  • 3008111bcd added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet Kip Macsai-Goren 2021-07-23 16:02:42 -0400
  • 381a93b45b added sfence to legal instructions, zeroed out rom file to populate for tests Kip Macsai-Goren 2021-07-23 15:55:08 -0400
  • 221b8097d6 uppdated makefile to not simulate pmp/pma tests with ovpsim Kip Macsai-Goren 2021-07-23 15:29:03 -0400
  • 63f8a97939 fixed write pmp csr test, added physical exe test, fixed instr fault return problem, general light cleanup Kip Macsai-Goren 2021-07-23 15:27:54 -0400
  • da9ead2d95 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-23 15:16:01 -0400
  • b093bf84a4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-23 14:00:52 -0400
  • 0e64b99dc0 testbench workaround for QEMU's SSTATUS XLEN bits bbracker 2021-07-23 14:00:44 -0400
  • f3579032bd Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's kipmacsaigoren 2021-07-23 11:57:58 -0500
  • 5d2b30e332 Removed LEVELx states from HPTW David Harris 2021-07-23 08:11:15 -0400
  • 9939c66a1f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-22 19:42:32 -0500
  • 3e916da36e Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register, SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select this SavedReadDataM so that the CPU can capture it. Ross Thompson 2021-07-22 19:42:19 -0500
  • 52faa22774 include SFENCE.VMA in legal instructions Kip Macsai-Goren 2021-07-22 20:24:24 -0400
  • 5faae637ce removed backups that are no longer needed Kip Macsai-Goren 2021-07-22 20:23:17 -0400
  • 98660e0d19 Minor unpacking cleanup David Harris 2021-07-22 17:52:37 -0400
  • 551e3491af Moved the ReadDataW register into the datapath. The StallW from the hazard unit controls this. Previously it was in the dcache and controlled by both the HPTW and hazard unit. This caused an issue when the CPU expected the data to stay constant while stalled, but the HPTW was causing the data to be modified. Ross Thompson 2021-07-22 14:51:14 -0500
  • fbbfc799b9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-22 14:05:08 -0500
  • 9c90b4bdf7 Fixed bug with the itlb fault not dcache ptw ready state to ready state. Ross Thompson 2021-07-22 14:04:56 -0500
  • c9890afb7f Move Z sign swapping out of unpacker David Harris 2021-07-22 14:32:38 -0400
  • 31be570461 Move Z=0 mux out of unpacker. David Harris 2021-07-22 14:28:55 -0400
  • 63718cef8f Move Z=0 mux out of unpacker. David Harris 2021-07-22 14:22:28 -0400
  • 21a65f45cd Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. David Harris 2021-07-22 14:18:27 -0400
  • b53eb6d030 Simplify unpacker David Harris 2021-07-22 13:42:16 -0400
  • 19dac66264 Simplify unpacker David Harris 2021-07-22 13:40:42 -0400
  • 44141047ef Removed Assumed1 from FPU interface David Harris 2021-07-22 13:04:47 -0400
  • 3ad2170ffd Simplified interface to fclassify and fsgn (fixed) David Harris 2021-07-22 12:33:38 -0400
  • 5e155e4fd1 Simplified interface to fclassify and fsgn David Harris 2021-07-22 12:30:46 -0400
  • b4029a2848 Cleaned up icache and dcache. Ross Thompson 2021-07-22 11:06:44 -0500
  • 3dd89a7e62 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-22 10:38:24 -0500
  • 25a8920a69 Tested all numbers of ways for dcache 1, 2, 4, and 8. Ross Thompson 2021-07-22 10:38:07 -0500
  • d3059dd04c fix UART RX FIFO bug where tail pointer can overtake head pointer bbracker 2021-07-22 02:09:41 -0400
  • 57a2917997 make address translator signals visible in waveview bbracker 2021-07-21 20:07:49 -0400
  • cca16cc5b4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-21 20:07:03 -0400
  • 6e460c5032 replace physical address checking with virtual address checking because address translator is broken bbracker 2021-07-21 19:47:13 -0400
  • 25391bcfce hardcoded hack to fix missing STVEC vector bbracker 2021-07-21 19:34:57 -0400
  • dac93bb366 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-21 16:44:32 -0500
  • c69a5dc8a6 fixed issue with tlbflush remaining high during a stalled sfence instruction Kip Macsai-Goren 2021-07-21 17:43:36 -0400
  • 71375ba655 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-21 16:39:07 -0500
  • 7785401281 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-21 14:56:30 -0500
  • 313bc5255c Improved address bus names and usages in the walker, dcache, and tlbs. Merge branch 'walkerEnhance' into main Ross Thompson 2021-07-21 14:55:09 -0500
  • 310b454fa1 Added comment about better muxing. Ross Thompson 2021-07-21 14:40:14 -0500
  • 5860f147d4 4 way set associative is now working. Ross Thompson 2021-07-21 14:01:14 -0500
  • 1c1ae2d61e removed remaining 32 bit loads/stores with 64 bit ones. Kip Macsai-Goren 2021-07-21 14:45:22 -0400
  • 4eaf95de60 Fixed TLB parameterization and valid bit flop to correctly do instr page faults Kip Macsai-Goren 2021-07-21 14:44:43 -0400
  • 01f0b4e5df FDIV and FSQRT work Katherine Parry 2021-07-21 14:08:14 -0400
  • f9c0d33773 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-21 13:04:11 -0400
  • 82ce85c24f progress on recovering from QEMU's errors bbracker 2021-07-21 13:00:32 -0400
  • e0990535e1 Fixed remaining bugs in 2 way set associative dcache. Ross Thompson 2021-07-21 10:35:23 -0500
  • 3f780f012a Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. Also forgot to include cacheLRU.sv file. Ross Thompson 2021-07-20 23:17:42 -0500
  • b9081e514c FMA parameterized Katherine Parry 2021-07-20 22:04:21 -0400
  • 2cdb019602 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-20 21:04:53 -0400
  • 1f4718192c light cleanup Kip Macsai-Goren 2021-07-20 20:49:07 -0400
  • 656c1c9949 added new execution tests that should work with dcache memory non-syncness with 'real memory'. They make, but don't pass regression yet Kip Macsai-Goren 2021-07-20 20:47:20 -0400
  • bac10a2198 added new executable test, cheange PTE to test library Kip Macsai-Goren 2021-07-20 20:39:00 -0400
  • 14e949d6e3 Partially working 2 way set associative d cache. Ross Thompson 2021-07-20 17:51:42 -0500
  • f9b6bd91f5 fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk bbracker 2021-07-20 17:55:44 -0400
  • 7e83fdff19 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-20 17:01:09 -0400
  • a02694a529 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-20 15:04:13 -0400