forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
7785401281
@ -78,8 +78,6 @@
|
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// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
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`define BOOTTIM_SUPPORTED 1'b1
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//`define BOOTTIM_RANGE 56'h00003FFF
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//`define BOOTTIM_BASE 56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
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`define BOOTTIM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
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`define BOOTTIM_RANGE 56'h00000FFF
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`define TIM_SUPPORTED 1'b1
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@ -49,9 +49,9 @@
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`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
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// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
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`define FLEN (`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
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`define NE (`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
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`define NF (`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
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`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
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`define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
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`define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
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// Disable spurious Verilator warnings
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@ -30,10 +30,11 @@ outDir="../linux-testvectors"
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# - Makes qemu_in_gdb_format.txt
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# - Splits qemu_in_gdb_format.txt into chunks of 100,000 instrs
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#cat $intermedDir/qemu_output.txt | ./parse_qemu.py >$intermedDir/qemu_in_gdb_format.txt
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cd $intermedDir
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split -d -l 5000000 ./qemu_in_gdb_format.txt --verbose
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cd ../../testvector-generation
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#cd $intermedDir
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#split -d -l 5000000 ./qemu_in_gdb_format.txt --verbose
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#cd ../../testvector-generation
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# Uncomment this version for parse_gdb_output.py debugging
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# - Uses qemu_in_gdb_format.txt
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# - Makes testvectors#cat $intermedDir/qemu_in_gdb_format.txt | ./parse_gdb_output.py "$outDir"
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# - Makes testvectors
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#cat $intermedDir/qemu_in_gdb_format.txt | ./parse_gdb_output.py "$outDir"
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@ -1,10 +1,12 @@
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set pagination off
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file ../buildroot-image-output/fw_jump.elf
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target extended-remote :1237
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b irqchip_plic_warm_init
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b *0x80200040
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c
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file ../buildroot-image-output/vmlinux
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b plic_init
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c
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#b irqchip_plic_warm_init
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#c
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#b plic_init
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#c
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b do_idle
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c
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@ -36,12 +36,15 @@ def printCSRs():
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def parseCSRs(l):
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global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs
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if l.strip() and (not l.startswith("Disassembler")) and (not l.startswith("Please")) and not inPageFault:
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if l.strip() and (not l.startswith("Disassembler")) and (not l.startswith("Please")):
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# If we've hit the register file
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if l.startswith(' x0/zero'):
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parseState = "regFile"
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instr = instrs[CSRs["pc"]]
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printPC(instr)
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if not inPageFault:
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instr = instrs[CSRs["pc"]]
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printPC(instr)
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parseRegs(l)
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# If we've hit a CSR
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else:
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csr = l.split()[0]
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val = int(l.split()[1],16)
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@ -64,11 +67,16 @@ def parseCSRs(l):
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# However SEPC and STVAL do get corrupted upon exiting
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if endPageFault and ((csr == 'sepc') or (csr == 'stval')):
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CSRs[csr] = returnAdr
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pageFaultCSRs[csr] = val
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elif pageFaultCSRs and (csr in pageFaultCSRs):
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if (val != pageFaultCSRs[csr]):
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del pageFaultCSRs[csr]
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CSRs[csr] = val
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else:
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CSRs[csr] = val
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def parseRegs(l):
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global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs
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global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, pageFaultRegs
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if "pc" in l:
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printCSRs()
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# New non-disassembled instruction
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@ -86,6 +94,7 @@ def parseRegs(l):
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val = int(s[i+1], 16)
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if inPageFault:
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pageFaultRegs[reg] = val
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sys.stderr.write(str(pageFaultRegs))
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else:
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if pageFaultRegs and (reg in pageFaultRegs):
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if (val != pageFaultRegs[reg]):
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@ -110,9 +119,10 @@ for l in fileinput.input():
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elif (parseState == "instr") and l.startswith('0x'):
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if "out of bounds" in l:
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sys.stderr.write("Detected QEMU page fault error\n")
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beginPageFault = ~(inPageFault)
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beginPageFault = not inPageFault
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if beginPageFault:
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returnAdr = int(l.split()[0][2:-1], 16)
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sys.stderr.write('Saving SEPC of '+hex(returnAdr)+'\n')
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inPageFault = 1
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else:
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endPageFault = inPageFault
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@ -23,6 +23,7 @@
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///////////////////////////////////////////
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`include "wally-config.vh"
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// `include "../../../config/rv64icfd/wally-config.vh"
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module fma(
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input logic clk,
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@ -33,11 +34,11 @@ module fma(
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input logic [2:0] FOpCtrlM, FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic XSgnE, YSgnE, ZSgnE,
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input logic [10:0] XExpE, YExpE, ZExpE,
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input logic [51:0] XFracE, YFracE, ZFracE,
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input logic [`NE-1:0] XExpE, YExpE, ZExpE,
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input logic [`NF-1:0] XFracE, YFracE, ZFracE,
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input logic XSgnM, YSgnM, ZSgnM,
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input logic [10:0] XExpM, YExpM, ZExpM,
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input logic [51:0] XFracM, YFracM, ZFracM,
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input logic [`NE-1:0] XExpM, YExpM, ZExpM,
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input logic [`NF-1:0] XFracM, YFracM, ZFracM,
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input logic XAssumed1E, YAssumed1E, ZAssumed1E,
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input logic XDenormE, YDenormE, ZDenormE,
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input logic XZeroE, YZeroE, ZZeroE,
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@ -46,13 +47,13 @@ module fma(
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input logic XZeroM, YZeroM, ZZeroM,
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input logic XInfM, YInfM, ZInfM,
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input logic [10:0] BiasE,
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output logic [63:0] FMAResM,
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output logic [`FLEN-1:0] FMAResM,
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output logic [4:0] FMAFlgM);
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logic [105:0] ProdManE, ProdManM;
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logic [161:0] AlignedAddendE, AlignedAddendM;
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logic [12:0] ProdExpE, ProdExpM;
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logic [2*`NF+1:0] ProdManE, ProdManM;
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logic [3*`NF+5:0] AlignedAddendE, AlignedAddendM;
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logic [`NE+1:0] ProdExpE, ProdExpM;
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logic AddendStickyE, AddendStickyM;
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logic KillProdE, KillProdM;
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@ -128,7 +129,7 @@ module fma1(
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assign AlignCnt = ProdExpE - ZExpE - ZDenormE;
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// Defualt Addition without shifting
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// | 55'b0 | 106'b(product) | 2'b0 |
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// | 54'b0 | 106'b(product) | 2'b0 |
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// |1'b0| addnend |
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// the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...)
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@ -140,7 +141,7 @@ module fma1(
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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if ($signed(AlignCnt) <= /*$signed(-13'd56)*/-(`NF+4)) begin
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if ($signed(AlignCnt) <= $signed(-(`NF+4))) begin
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KillProdE = 1;
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ZManShifted = ZManPreShifted;//{107'b0, {~ZAssumed1E, ZFrac}, 54'b0};
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AddendStickyE = ~(XZeroE|YZeroE);
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@ -149,19 +150,19 @@ module fma1(
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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end else if($signed(AlignCnt) <= 0) begin
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end else if($signed(AlignCnt) <= $signed(0)) begin
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KillProdE = 0;
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ZManShifted = ZManPreShifted << -AlignCnt;
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AddendStickyE = |(ZManShifted[51:0]);
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AddendStickyE = |(ZManShifted[`NF-1:0]);
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// If the Addend is shifted right (positive AlignCnt)
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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end else if ($signed(AlignCnt)<=(2*`NF+2)) begin
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end else if ($signed(AlignCnt)<=$signed(2*`NF+1)) begin
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KillProdE = 0;
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ZManShifted = ZManPreShifted >> AlignCnt;
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AddendStickyE = |(ZManShifted[51:0]);
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AddendStickyE = |(ZManShifted[`NF-1:0]);
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// If the addend is too small to effect the addition
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// - The addend has to shift two past the end of the addend to be considered too small
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@ -176,47 +177,47 @@ module fma1(
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end
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end
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assign AlignedAddendE = ZManShifted[(4*`NF+5):`NF];
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assign AlignedAddendE = ZManShifted[4*`NF+5:`NF];
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endmodule
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module fma2(
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input logic XSgnM, YSgnM, ZSgnM,
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input logic [10:0] XExpM, YExpM, ZExpM,
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input logic [51:0] XFracM, YFracM, ZFracM,
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input logic [`NE-1:0] XExpM, YExpM, ZExpM,
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input logic [`NF-1:0] XFracM, YFracM, ZFracM,
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic [2:0] FOpCtrlM, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
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input logic FmtM, // precision 1 = double 0 = single
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input logic [105:0] ProdManM, // 1.X frac * 1.Y frac
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input logic [161:0] AlignedAddendM, // Z aligned for addition
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input logic [12:0] ProdExpM, // X exponent + Y exponent - bias
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input logic [2*`NF+1:0] ProdManM, // 1.X frac * 1.Y frac
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input logic [3*`NF+5:0] AlignedAddendM, // Z aligned for addition
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input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
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input logic AddendStickyM, // sticky bit that is calculated during alignment
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input logic KillProdM, // set the product to zero before addition if the product is too small to matter
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input logic XZeroM, YZeroM, ZZeroM, // inputs are zero
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input logic XInfM, YInfM, ZInfM, // inputs are infinity
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input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN
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input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs
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output logic [63:0] FMAResM, // FMA final result
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output logic [`FLEN-1:0] FMAResM, // FMA final result
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output logic [4:0] FMAFlgM); // FMA flags {invalid, divide by zero, overflow, underflow, inexact}
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logic [51:0] ResultFrac; // Result fraction
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logic [10:0] ResultExp; // Result exponent
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logic [`NF-1:0] ResultFrac; // Result fraction
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logic [`NE-1:0] ResultExp; // Result exponent
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logic ResultSgn; // Result sign
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logic PSgn; // product sign
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logic [105:0] ProdMan2; // product being added
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logic [162:0] AlignedAddend2; // possibly inverted aligned Z
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logic [161:0] Sum; // positive sum
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logic [162:0] PreSum; // possibly negitive sum
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logic [12:0] SumExp; // exponent of the normalized sum
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logic [12:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results
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logic [12:0] SumExpTmpMinus1; // SumExpTmp-1
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logic [12:0] FullResultExp; // ResultExp with bits to determine sign and overflow
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logic [54:0] NormSum; // normalized sum
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logic [161:0] SumShifted; // sum shifted for normalization
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logic [8:0] NormCnt; // output of the leading zero detector
|
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logic [2*`NF+1:0] ProdMan2; // product being added
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||||
logic [3*`NF+6:0] AlignedAddend2; // possibly inverted aligned Z
|
||||
logic [3*`NF+5:0] Sum; // positive sum
|
||||
logic [3*`NF+6:0] PreSum; // possibly negitive sum
|
||||
logic [`NE+1:0] SumExp; // exponent of the normalized sum
|
||||
logic [`NE+1:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results
|
||||
logic [`NE+1:0] SumExpTmpMinus1; // SumExpTmp-1
|
||||
logic [`NE+1:0] FullResultExp; // ResultExp with bits to determine sign and overflow
|
||||
logic [`NF+2:0] NormSum; // normalized sum
|
||||
logic [3*`NF+5:0] SumShifted; // sum shifted for normalization
|
||||
logic [8:0] NormCnt; // output of the leading zero detector //***change this later
|
||||
logic NormSumSticky; // sticky bit calulated from the normalized sum
|
||||
logic SumZero; // is the sum zero
|
||||
logic NegSum; // is the sum negitive
|
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@ -226,18 +227,18 @@ module fma2(
|
||||
logic Plus1, Minus1, CalcPlus1, CalcMinus1; // do you add or subtract one for rounding
|
||||
logic UfPlus1, UfCalcPlus1; // do you add one (for determining underflow flag)
|
||||
logic Invalid,Underflow,Overflow,Inexact; // flags
|
||||
logic [8:0] DenormShift; // right shift if the result is denormalized
|
||||
logic [8:0] DenormShift; // right shift if the result is denormalized //***change this later
|
||||
logic SubBySmallNum; // was there supposed to be a subtraction by a small number
|
||||
logic [63:0] Addend; // value to add (Z or zero)
|
||||
logic [`FLEN-1:0] Addend; // value to add (Z or zero)
|
||||
logic ZeroSgn; // the result's sign if the sum is zero
|
||||
logic ResultSgnTmp; // the result's sign assuming the result is not zero
|
||||
logic Guard, Round, LSBNormSum; // bits needed to determine rounding
|
||||
logic UfGuard, UfRound, UfLSBNormSum; // bits needed to determine rounding for underflow flag
|
||||
logic [12:0] MaxExp; // maximum value of the exponent
|
||||
logic [12:0] FracLen; // length of the fraction
|
||||
logic [`NE+1:0] MaxExp; // maximum value of the exponent
|
||||
logic [`NE+1:0] FracLen; // length of the fraction
|
||||
logic SigNaN; // is an input a signaling NaN
|
||||
logic UnderflowFlag; // Underflow singal used in FMAFlgM (used to avoid a circular depencency)
|
||||
logic [63:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
|
||||
logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
|
||||
|
||||
|
||||
|
||||
@ -259,17 +260,17 @@ module fma2(
|
||||
// Choose an inverted or non-inverted addend - the one is added later
|
||||
assign AlignedAddend2 = InvZ ? ~{1'b0, AlignedAddendM} : {1'b0, AlignedAddendM};
|
||||
// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
|
||||
assign ProdMan2 = KillProdM ? 106'b0 : ProdManM;
|
||||
assign ProdMan2 = KillProdM ? 0 : ProdManM;
|
||||
|
||||
// Do the addition
|
||||
// - add one to negate if the added was inverted
|
||||
// - the 2 extra bits at the begining and end are needed for rounding
|
||||
assign PreSum = AlignedAddend2 + {55'b0, ProdMan2, 2'b0} + {162'b0, InvZ};
|
||||
assign PreSum = AlignedAddend2 + {ProdMan2, 2'b0} + InvZ;
|
||||
|
||||
// Is the sum negitive
|
||||
assign NegSum = PreSum[162];
|
||||
assign NegSum = PreSum[3*`NF+6];
|
||||
// If the sum is negitive, negate the sum.
|
||||
assign Sum = NegSum ? -PreSum[161:0] : PreSum[161:0];
|
||||
assign Sum = NegSum ? -PreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
|
||||
|
||||
|
||||
|
||||
@ -284,7 +285,7 @@ module fma2(
|
||||
logic [8:0] i;
|
||||
always_comb begin
|
||||
i = 0;
|
||||
while (~Sum[161-i] && $unsigned(i) <= $unsigned(9'd161)) i = i+1; // search for leading one
|
||||
while (~Sum[3*`NF+5-i] && $unsigned(i) <= $unsigned(3*`NF+5)) i = i+1; // search for leading one
|
||||
NormCnt = i+1; // compute shift count
|
||||
end
|
||||
|
||||
@ -306,26 +307,26 @@ module fma2(
|
||||
assign SumZero = ~(|Sum);
|
||||
|
||||
// determine the length of the fraction based on precision
|
||||
assign FracLen = FmtM ? 13'd52 : 13'd23;
|
||||
assign FracLen = FmtM ? `NF : 13'd23;
|
||||
|
||||
// Determine if the result is denormal
|
||||
assign SumExpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCnt} - 13'd56);
|
||||
assign SumExpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCnt} - (`NF+4));
|
||||
assign ResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
|
||||
|
||||
// Determine the shift needed for denormal results
|
||||
assign SumExpTmpMinus1 = SumExpTmp-1;
|
||||
assign DenormShift = ResultDenorm ? SumExpTmpMinus1[8:0] : 9'b0;
|
||||
assign DenormShift = ResultDenorm ? SumExpTmpMinus1[8:0] : 0; //*** change this when changing the size of DenormShift also change to an and opperation
|
||||
|
||||
// Normalize the sum
|
||||
assign SumShifted = SumZero ? 162'b0 : Sum << NormCnt+DenormShift;
|
||||
assign NormSum = SumShifted[161:107];
|
||||
assign SumShifted = SumZero ? 0 : Sum << NormCnt+DenormShift; //*** fix mux's with constants in them
|
||||
assign NormSum = SumShifted[3*`NF+5:2*`NF+3];
|
||||
// Calculate the sticky bit
|
||||
assign NormSumSticky = FmtM ? (|SumShifted[107:0]) : (|SumShifted[136:0]);
|
||||
assign NormSumSticky = FmtM ? (|SumShifted[2*`NF+3:0]) : (|SumShifted[136:0]);
|
||||
assign Sticky = AddendStickyM | NormSumSticky;
|
||||
|
||||
// Determine sum's exponent
|
||||
assign SumExp = SumZero ? 13'b0 :
|
||||
ResultDenorm ? 13'b0 :
|
||||
assign SumExp = SumZero ? 0 : //***again fix mux
|
||||
ResultDenorm ? 0 :
|
||||
SumExpTmp;
|
||||
|
||||
|
||||
@ -412,14 +413,14 @@ module fma2(
|
||||
assign Minus1 = CalcMinus1 & (Sticky | UfGuard | Guard | Round);
|
||||
|
||||
// Compute rounded result
|
||||
logic [64:0] RoundAdd;
|
||||
logic [51:0] NormSumTruncated;
|
||||
assign RoundAdd = FmtM ? Minus1 ? {65{1'b1}} : {64'b0, Plus1} :
|
||||
logic [`FLEN:0] RoundAdd; //*** move this up
|
||||
logic [`NF-1:0] NormSumTruncated;
|
||||
assign RoundAdd = FmtM ? Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1} :
|
||||
Minus1 ? {{36{1'b1}}, 29'b0} : {35'b0, Plus1, 29'b0};
|
||||
assign NormSumTruncated = FmtM ? NormSum[54:3] : {NormSum[54:32], 29'b0};
|
||||
assign NormSumTruncated = FmtM ? NormSum[`NF+2:3] : {NormSum[54:32], 29'b0};
|
||||
|
||||
assign {FullResultExp, ResultFrac} = {SumExp, NormSumTruncated} + RoundAdd;
|
||||
assign ResultExp = FullResultExp[10:0];
|
||||
assign ResultExp = FullResultExp[`NE-1:0];
|
||||
|
||||
|
||||
|
||||
@ -457,18 +458,18 @@ module fma2(
|
||||
// 1) any input is a signaling NaN
|
||||
// 2) Inf - Inf (unless x or y is NaN)
|
||||
// 3) 0 * Inf
|
||||
assign MaxExp = FmtM ? 13'd2047 : 13'd255;
|
||||
assign MaxExp = FmtM ? {`NE{1'b1}} : 13'd255;
|
||||
assign SigNaN = XSNaNM | YSNaNM | ZSNaNM;
|
||||
assign Invalid = SigNaN | ((XInfM || YInfM) & ZInfM & (PSgn ^ ZSgnM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM);
|
||||
|
||||
// Set Overflow flag if the number is too big to be represented
|
||||
// - Don't set the overflow flag if an overflowed result isn't outputed
|
||||
assign Overflow = FullResultExp >= MaxExp & ~FullResultExp[12]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
|
||||
assign Overflow = FullResultExp >= MaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
|
||||
|
||||
// Set Underflow flag if the number is too small to be represented in normal numbers
|
||||
// - Don't set the underflow flag if the result is exact
|
||||
assign Underflow = (SumExp[12] | ((SumExp == 0) & (Round|Guard|Sticky|UfGuard)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
|
||||
assign UnderflowFlag = (FullResultExp[12] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Guard|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
|
||||
assign Underflow = (SumExp[`NE+1] | ((SumExp == 0) & (Round|Guard|Sticky|UfGuard)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
|
||||
assign UnderflowFlag = (FullResultExp[`NE+1] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Guard|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
|
||||
// Set Inexact flag if the result is diffrent from what would be outputed given infinite precision
|
||||
// - Don't set the underflow flag if an underflowed result isn't outputed
|
||||
assign Inexact = (Sticky|UfGuard|Overflow|Guard|Round|Underflow)&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
|
||||
@ -489,23 +490,23 @@ module fma2(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Select the result
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XFracM[50:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XFracM[50:29]};
|
||||
assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YFracM[50:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YFracM[50:29]};
|
||||
assign ZNaNResult = FmtM ? {ZSgnM, ZExpM, 1'b1, ZFracM[50:0]} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], 1'b1, ZFracM[50:29]};
|
||||
assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, 11'h7fe, {52{1'b1}}} :
|
||||
{ResultSgn, 11'h7ff, 52'b0} :
|
||||
assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XFracM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XFracM[50:29]};
|
||||
assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YFracM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YFracM[50:29]};
|
||||
assign ZNaNResult = FmtM ? {ZSgnM, ZExpM, 1'b1, ZFracM[`NF-2:0]} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], 1'b1, ZFracM[50:29]};
|
||||
assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} :
|
||||
{ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :
|
||||
((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} :
|
||||
{{32{1'b1}}, ResultSgn, 8'hff, 23'b0};
|
||||
assign InvalidResult = FmtM ? {ResultSgn, 11'h7ff, 1'b1, 51'b0} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
|
||||
assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZFracM} - {62'b0, (Minus1&AddendStickyM)}} + {62'b0, (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[7:0], ZFracM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
|
||||
assign UnderflowResult = FmtM ? {ResultSgn, 63'b0} + {63'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))} : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
|
||||
assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZFracM} - (Minus1&AddendStickyM) + (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[7:0], ZFracM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
|
||||
assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + (CalcPlus1&(AddendStickyM|FrmM[1])) : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
assign FMAResM = XNaNM ? XNaNResult :
|
||||
YNaNM ? YNaNResult :
|
||||
ZNaNM ? ZNaNResult :
|
||||
Invalid ? InvalidResult : // has to be before inf
|
||||
XInfM ? FmtM ? {PSgn, XExpM, XFracM} : {{32{1'b1}}, PSgn, XExpM[7:0], XFracM[51:29]} :
|
||||
XInfM ? FmtM ? {PSgn, YExpM, YFracM} : {{32{1'b1}}, PSgn, YExpM[7:0], YFracM[51:29]} :
|
||||
XInfM ? FmtM ? {ZSgnM, ZExpM, ZFracM} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], ZFracM[51:29]} :
|
||||
YInfM ? FmtM ? {PSgn, YExpM, YFracM} : {{32{1'b1}}, PSgn, YExpM[7:0], YFracM[51:29]} :
|
||||
ZInfM ? FmtM ? {ZSgnM, ZExpM, ZFracM} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], ZFracM[51:29]} :
|
||||
Overflow ? OverflowResult :
|
||||
KillProdM ? KillProdResult : // has to be after Underflow
|
||||
Underflow & ~ResultDenorm ? UnderflowResult :
|
||||
|
||||
@ -204,7 +204,7 @@ module fpu (
|
||||
fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .done(FDivSqrtDoneE), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]),
|
||||
.P(~FmtE), .FDivBusyE, .HoldInputs,
|
||||
.OvEn(1'b1), .UnEn(1'b1),
|
||||
.start(FDivStartE), .reset, .clk(~clk), .AS_Result(FDivResultM), .Flags(FDivSqrtFlgM));
|
||||
.start(FDivStartE), .reset, .clk(fpdivClk), .AS_Result(FDivResultM), .Flags(FDivSqrtFlgM));
|
||||
|
||||
// .DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .DivInput1E, .DivInput2E,
|
||||
// .FrmE, .DivOvEn(1'b1), .DivUnEn(1'b1), .FDivStartE, .FDivResultM, .FDivSqrtFlgM,
|
||||
|
||||
@ -476,7 +476,7 @@ module fsm (done, load_rega, load_regb, load_regc,
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b110;
|
||||
sel_muxr = 1'b1;
|
||||
NEXT_STATE = S27;
|
||||
NEXT_STATE = S26;
|
||||
end
|
||||
S26: // done
|
||||
begin
|
||||
|
||||
@ -56,9 +56,9 @@ module unpacking (
|
||||
assign YNaNE = YExpMaxE & ~YFracZero;
|
||||
assign ZNaNE = ZExpMaxE & ~ZFracZero;
|
||||
|
||||
assign XSNaNE = XNaNE&~XExpE[51];
|
||||
assign YSNaNE = YNaNE&~YExpE[51];
|
||||
assign ZSNaNE = ZNaNE&~ZExpE[51];
|
||||
assign XSNaNE = XNaNE&~XFracE[51];
|
||||
assign YSNaNE = YNaNE&~YFracE[51];
|
||||
assign ZSNaNE = ZNaNE&~ZFracE[51];
|
||||
|
||||
assign XDenormE = XExpZero & ~XFracZero;
|
||||
assign YDenormE = YExpZero & ~YFracZero;
|
||||
|
||||
@ -87,31 +87,32 @@ module uncore (
|
||||
generate
|
||||
// tightly integrated memory
|
||||
dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
|
||||
//if (`BOOTTIM_SUPPORTED) *** restore when naming is figured out
|
||||
if (`BOOTTIM_SUPPORTED) begin : bootdtim
|
||||
dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
|
||||
end
|
||||
|
||||
// memory-mapped I/O peripherals
|
||||
if (`CLINT_SUPPORTED == 1)
|
||||
if (`CLINT_SUPPORTED == 1) begin : clint
|
||||
clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*);
|
||||
else begin
|
||||
end else begin : clint
|
||||
assign MTIME_CLINT = 0; assign MTIMECMP_CLINT = 0;
|
||||
assign TimerIntM = 0; assign SwIntM = 0;
|
||||
end
|
||||
if (`PLIC_SUPPORTED == 1)
|
||||
if (`PLIC_SUPPORTED == 1) begin : plic
|
||||
plic plic(.HADDR(HADDR[27:0]), .*);
|
||||
else begin
|
||||
end else begin : plic
|
||||
assign ExtIntM = 0;
|
||||
end
|
||||
if (`GPIO_SUPPORTED == 1)
|
||||
if (`GPIO_SUPPORTED == 1) begin : gpio
|
||||
gpio gpio(.HADDR(HADDR[7:0]), .*);
|
||||
else begin
|
||||
end else begin : gpio
|
||||
assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
|
||||
end
|
||||
if (`UART_SUPPORTED == 1)
|
||||
if (`UART_SUPPORTED == 1) begin : uart
|
||||
uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
|
||||
.DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1),
|
||||
.RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
|
||||
else begin
|
||||
end else begin : uart
|
||||
assign UARTSout = 0; assign UARTIntr = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
@ -121,7 +121,7 @@ string tests32f[] = '{
|
||||
"rv64d/I-FLD-01", "2420",
|
||||
"rv64d/I-FMV-X-D-01", "2000",
|
||||
"rv64d/I-FMV-D-X-01", "2000",
|
||||
// "rv64d/I-FDIV-D-01", "2000",
|
||||
"rv64d/I-FDIV-D-01", "2000",
|
||||
"rv64d/I-FCVT-D-L-01", "2000",
|
||||
"rv64d/I-FCVT-D-LU-01", "2000",
|
||||
"rv64d/I-FCVT-D-S-01", "2000",
|
||||
@ -147,7 +147,7 @@ string tests32f[] = '{
|
||||
"rv64d/I-FSGNJ-D-01", "2000",
|
||||
"rv64d/I-FSGNJN-D-01", "2000",
|
||||
"rv64d/I-FSGNJX-D-01", "2000",
|
||||
// "rv64d/I-FSQRT-D-01", "2000",
|
||||
"rv64d/I-FSQRT-D-01", "2000",
|
||||
"rv64d/I-FSUB-D-01", "2000"
|
||||
};
|
||||
|
||||
@ -753,6 +753,7 @@ module riscvassertions();
|
||||
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $error("Multiple Instruction Cache ways not yet implemented");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`TIM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF");
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
|
||||
module testbench();
|
||||
|
||||
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0900000; // # of instructions at which to turn on waves in graphical sim
|
||||
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3160000; // # of instructions at which to turn on waves in graphical sim
|
||||
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
@ -140,7 +140,7 @@ module testbench();
|
||||
end
|
||||
// initial loading of memories
|
||||
initial begin
|
||||
$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
|
||||
$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
|
||||
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
||||
@ -222,24 +222,24 @@ module testbench();
|
||||
`SCAN_PC(data_file_PCF, scan_file_PCF, PCtextF, PCtextF2, InstrFExpected, PCFexpected);
|
||||
`SCAN_PC(data_file_PCD, scan_file_PCD, PCtextD, PCtextD2, InstrDExpected, PCDexpected);
|
||||
|
||||
// NOP out certain instructions
|
||||
if(dut.hart.ifu.PCD===PCDexpected) begin
|
||||
if((dut.hart.ifu.PCD == 32'h80001dc6) || // for now, NOP out any stores to PLIC
|
||||
(dut.hart.ifu.PCD == 32'h80001de0) ||
|
||||
(dut.hart.ifu.PCD == 32'h80001de2)) begin
|
||||
$display("warning: NOPing out %s at PCD=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time);
|
||||
force InstrDExpected = 32'b0010011;
|
||||
force dut.hart.ifu.InstrRawD = 32'b0010011;
|
||||
while (clk != 0) #1;
|
||||
while (clk != 1) #1;
|
||||
release dut.hart.ifu.InstrRawD;
|
||||
release InstrDExpected;
|
||||
warningCount += 1;
|
||||
forcedInstr = 1;
|
||||
end else begin
|
||||
forcedInstr = 0;
|
||||
end
|
||||
end
|
||||
// NOP out certain instructions <-- commented out because no duh hardcoded addressses break easily
|
||||
//if(dut.hart.ifu.PCD===PCDexpected) begin
|
||||
// if((dut.hart.ifu.PCD == 32'h80001dc6) || // for now, NOP out any stores to PLIC
|
||||
// (dut.hart.ifu.PCD == 32'h80001de0) ||
|
||||
// (dut.hart.ifu.PCD == 32'h80001de2)) begin
|
||||
// $display("warning: NOPing out %s at PCD=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time);
|
||||
// force InstrDExpected = 32'b0010011;
|
||||
// force dut.hart.ifu.InstrRawD = 32'b0010011;
|
||||
// while (clk != 0) #1;
|
||||
// while (clk != 1) #1;
|
||||
// release dut.hart.ifu.InstrRawD;
|
||||
// release InstrDExpected;
|
||||
// warningCount += 1;
|
||||
// forcedInstr = 1;
|
||||
// end else begin
|
||||
// forcedInstr = 0;
|
||||
// end
|
||||
//end
|
||||
|
||||
// Increment instruction count
|
||||
if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
|
||||
@ -260,7 +260,7 @@ module testbench();
|
||||
|
||||
// Check if PCD is going to be flushed due to a branch or jump
|
||||
if (`BPRED_ENABLED) begin
|
||||
PCDwrong = dut.hart.hzu.FlushD || (PCtextE.substr(0,3) == "mret"); //Old version: dut.hart.ifu.bpred.bpred.BPPredWrongE; <-- This old version failed to account for MRET.
|
||||
PCDwrong = dut.hart.hzu.FlushD || (PCtextE.substr(0,3) == "mret") || dut.hart.priv.InstrPageFaultF || dut.hart.priv.InstrPageFaultD || dut.hart.priv.InstrPageFaultE || dut.hart.priv.InstrPageFaultM;
|
||||
end
|
||||
|
||||
// Check PCD, InstrD
|
||||
@ -283,10 +283,10 @@ module testbench();
|
||||
scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
|
||||
scan_file_memR = $fscanf(data_file_memR, "%x\n", readDataExpected);
|
||||
// Next force a timer interrupt (*** this may later need generalizing)
|
||||
force dut.uncore.genblk1.clint.MTIME = dut.uncore.genblk1.clint.MTIMECMP + 1;
|
||||
force dut.uncore.clint.clint.MTIME = dut.uncore.clint.clint.MTIMECMP + 1;
|
||||
while (clk != 0) #1;
|
||||
while (clk != 1) #1;
|
||||
release dut.uncore.genblk1.clint.MTIME;
|
||||
release dut.uncore.clint.clint.MTIME;
|
||||
end
|
||||
end
|
||||
end
|
||||
@ -526,6 +526,7 @@ module testbench();
|
||||
string MTVALstring = "MTVAL";
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||||
string SEPCstring = "SEPC";
|
||||
string SCAUSEstring = "SCAUSE";
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||||
string STVALstring = "STVAL";
|
||||
string SSTATUSstring = "SSTATUS";
|
||||
|
||||
logic [63:0] expectedCSR;
|
||||
@ -556,6 +557,7 @@ module testbench();
|
||||
if (``CSR``name == MTVALstring) #3; \
|
||||
if (``CSR``name == SEPCstring) #1; \
|
||||
if (``CSR``name == SCAUSEstring) #2; \
|
||||
if (``CSR``name == STVALstring) #3; \
|
||||
if (``CSR``name == SSTATUSstring) #3; \
|
||||
scan_file_csr = $fscanf(data_file_csr, "%s\n", expectedCSRname); \
|
||||
scan_file_csr = $fscanf(data_file_csr, "%x\n", expectedCSR); \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user