hardcoded hack to fix missing STVEC vector

This commit is contained in:
bbracker 2021-07-21 19:34:57 -04:00
parent f9c0d33773
commit 25391bcfce
6 changed files with 40 additions and 9 deletions

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@ -23,7 +23,7 @@ outDir="../linux-testvectors"
# Uncomment this version to generate qemu_output.txt
# - Uses GDB script
# - Logs raw QEMU output to qemu_output.txt
#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
# Uncomment this version for parse_qemu.py debugging
# - Uses qemu_output.txt

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@ -0,0 +1,28 @@
#! /usr/bin/python3
import sys, fileinput
sys.stderr.write("reminder: fix_csrs.py is nothing but hardcoded hackery to combat QEMU's faulty printing")
csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
# just for now, since these CSRs aren't yet ready to be checked in testbench-linux
list(map(csrs.remove, ['fcsr','mhartid','pmpcfg0','pmpaddr0','mip']))
output_path = sys.argv[1]+'/'
print(f'output dir: {output_path}')
count = 0
csr = ''
with open('{}parsedCSRs.txt'.format(output_path), 'w') as fixedCSRs:
with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'r') as rawCSRs:
for l in rawCSRs:
fixedCSRs.write(l)
count += 1
if '---' in l:
count = 0
if (count%2 == 1): # every other line is CSR name
csr = l
else:
if ('stval' in csr) and ('8020007e' in l):
print('Adding stvec vector')
fixedCSRs.write('stvec\n')
fixedCSRs.write('ffffffff800000b0\n')

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@ -1,11 +1,14 @@
set pagination off
target extended-remote :1236
file ../buildroot-image-output/vmlinux
b do_idle
c
c
c
#b do_idle
#c
#c
#c
#c
b *0x80200040
c
stepi 10000
set confirm off
kill
q

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@ -12,3 +12,4 @@ outDir="../linux-testvectors"
# - Logs info needed by buildroot testbench
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
./fix_csrs.py "$outDir"

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@ -1,7 +1,7 @@
#! /usr/bin/python3
import sys, fileinput
sys.stderr.write("reminder: this script takes input from stdin\n")
sys.stderr.write("reminder: parse_gdb_output.py takes input from stdin\n")
csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
@ -17,7 +17,7 @@ try:
with open('{}parsedRegs.txt'.format(output_path), 'w') as wReg:
with open('{}parsedMemRead.txt'.format(output_path), 'w') as wMem:
with open('{}parsedMemWrite.txt'.format(output_path), 'w') as wMemW:
with open('{}parsedCSRs.txt'.format(output_path), 'w') as wCSRs:
with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'w') as wCSRs:
firstCSR = True
curCSRs = {}
lastRead = ''

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@ -1,7 +1,7 @@
#! /usr/bin/python3
import fileinput, sys
sys.stderr.write("reminder: this script takes input from stdin\n")
sys.stderr.write("reminder: parse_qemu.py takes input from stdin\n")
parseState = "idle"
beginPageFault = 0
inPageFault = 0
@ -94,7 +94,6 @@ def parseRegs(l):
val = int(s[i+1], 16)
if inPageFault:
pageFaultRegs[reg] = val
sys.stderr.write(str(pageFaultRegs))
else:
if pageFaultRegs and (reg in pageFaultRegs):
if (val != pageFaultRegs[reg]):