forked from Github_Repos/cvw
hardcoded hack to fix missing STVEC vector
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f9c0d33773
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@ -23,7 +23,7 @@ outDir="../linux-testvectors"
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# Uncomment this version to generate qemu_output.txt
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# - Uses GDB script
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# - Logs raw QEMU output to qemu_output.txt
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#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
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($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
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# Uncomment this version for parse_qemu.py debugging
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# - Uses qemu_output.txt
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28
wally-pipelined/linux-testgen/testvector-generation/fix_csrs.py
Executable file
28
wally-pipelined/linux-testgen/testvector-generation/fix_csrs.py
Executable file
@ -0,0 +1,28 @@
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#! /usr/bin/python3
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import sys, fileinput
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sys.stderr.write("reminder: fix_csrs.py is nothing but hardcoded hackery to combat QEMU's faulty printing")
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csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
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# just for now, since these CSRs aren't yet ready to be checked in testbench-linux
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list(map(csrs.remove, ['fcsr','mhartid','pmpcfg0','pmpaddr0','mip']))
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output_path = sys.argv[1]+'/'
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print(f'output dir: {output_path}')
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count = 0
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csr = ''
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with open('{}parsedCSRs.txt'.format(output_path), 'w') as fixedCSRs:
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with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'r') as rawCSRs:
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for l in rawCSRs:
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fixedCSRs.write(l)
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count += 1
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if '---' in l:
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count = 0
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if (count%2 == 1): # every other line is CSR name
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csr = l
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else:
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if ('stval' in csr) and ('8020007e' in l):
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print('Adding stvec vector')
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fixedCSRs.write('stvec\n')
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fixedCSRs.write('ffffffff800000b0\n')
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@ -1,11 +1,14 @@
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set pagination off
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target extended-remote :1236
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file ../buildroot-image-output/vmlinux
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b do_idle
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c
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c
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c
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#b do_idle
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#c
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#c
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#c
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#c
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b *0x80200040
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c
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stepi 10000
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set confirm off
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kill
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q
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@ -12,3 +12,4 @@ outDir="../linux-testvectors"
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# - Logs info needed by buildroot testbench
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($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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./fix_csrs.py "$outDir"
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@ -1,7 +1,7 @@
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#! /usr/bin/python3
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import sys, fileinput
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sys.stderr.write("reminder: this script takes input from stdin\n")
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sys.stderr.write("reminder: parse_gdb_output.py takes input from stdin\n")
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csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
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@ -17,7 +17,7 @@ try:
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with open('{}parsedRegs.txt'.format(output_path), 'w') as wReg:
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with open('{}parsedMemRead.txt'.format(output_path), 'w') as wMem:
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with open('{}parsedMemWrite.txt'.format(output_path), 'w') as wMemW:
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with open('{}parsedCSRs.txt'.format(output_path), 'w') as wCSRs:
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with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'w') as wCSRs:
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firstCSR = True
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curCSRs = {}
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lastRead = ''
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@ -1,7 +1,7 @@
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#! /usr/bin/python3
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import fileinput, sys
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sys.stderr.write("reminder: this script takes input from stdin\n")
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sys.stderr.write("reminder: parse_qemu.py takes input from stdin\n")
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parseState = "idle"
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beginPageFault = 0
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inPageFault = 0
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@ -94,7 +94,6 @@ def parseRegs(l):
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val = int(s[i+1], 16)
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if inPageFault:
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pageFaultRegs[reg] = val
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sys.stderr.write(str(pageFaultRegs))
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else:
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if pageFaultRegs and (reg in pageFaultRegs):
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if (val != pageFaultRegs[reg]):
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