forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
fbbfc799b9
@ -3,43 +3,18 @@
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module fclassify (
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input logic XSgnE,
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input logic [51:0] XFracE,
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input logic XNaNE,
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input logic XSNaNE,
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input logic XNormE,
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input logic XDenormE,
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input logic XZeroE,
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input logic XInfE,
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// input logic FmtE, // 0-Single 1-Double
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output logic [63:0] ClassResE
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);
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// logic XSgnE;
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// logic Inf, NaN, Zero, Norm, Denorm;
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logic PInf, PZero, PNorm, PDenorm;
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logic NInf, NZero, NNorm, NDenorm;
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// logic MaxExp, ExpZero, ManZero, FirstBitFrac;
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// Single and Double precision layouts
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// assign XSgnE = FmtE ? FSrcXE[63] : FSrcXE[31];
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// basic calculations for readabillity
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// assign ExpZero = FmtE ? ~|FSrcXE[62:52] : ~|FSrcXE[30:23];
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// assign MaxExp = FmtE ? &FSrcXE[62:52] : &FSrcXE[30:23];
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// assign ManZero = FmtE ? ~|FSrcXE[51:0] : ~|FSrcXE[22:0];
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// assign FirstBitFrac = FmtE ? FSrcXE[51] : FSrcXE[22];
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// determine the type of number
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// assign NaN = MaxExp & ~ManZero;
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// assign Inf = MaxExp & ManZero;
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// assign Zero = ExpZero & ManZero;
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// assign Denorm= ExpZero & ~ManZero;
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// assign Norm = ~ExpZero;
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// determine the sub categories
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// assign QNaN = FirstBitFrac&NaN;
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// assign SNaN = ~FirstBitFrac&NaN;
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assign PInf = ~XSgnE&XInfE;
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assign NInf = XSgnE&XInfE;
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assign PNorm = ~XSgnE&XNormE;
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@ -3,8 +3,7 @@
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module fcvt (
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input logic XSgnE,
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input logic [10:0] XExpE,
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input logic [51:0] XFracE,
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input logic XAssumed1E,
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input logic [52:0] XManE,
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input logic XZeroE,
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input logic XNaNE,
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input logic XInfE,
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@ -65,7 +64,8 @@ module fcvt (
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// assign Bias = FmtE ? 12'h3ff : 12'h7f;
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assign Res64 = ((FOpCtrlE==4'b1010 || FOpCtrlE==4'b1110) | (FmtE&(FOpCtrlE==4'b0001 | FOpCtrlE==4'b0101 | FOpCtrlE==4'b0000 | FOpCtrlE==4'b1001 | FOpCtrlE==4'b1101)));
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assign In64 = ((FOpCtrlE==4'b1001 || FOpCtrlE==4'b1101) | (FmtE&(FOpCtrlE==4'b0010 | FOpCtrlE==4'b0110 | FOpCtrlE==4'b1010 | FOpCtrlE==4'b1110) | (FOpCtrlE==4'b1101 & ~FmtE)));
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assign SubBits = In64 ? 8'd64 : 8'd32;
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//assign SubBits = In64 ? 8'd64 : 8'd32;
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assign SubBits = 8'd64;
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assign Bits = Res64 ? 8'd64 : 8'd32;
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// calulate the unbiased exponent
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@ -108,12 +108,12 @@ module fcvt (
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// select the shift value and amount based on operation (to fp or int)
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assign ShiftCnt = FOpCtrlE[1] ? ExpVal : LZResP;
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assign ShiftVal = FOpCtrlE[1] ? {{64-2{1'b0}}, XAssumed1E, XFracE} : {PosInt, 52'b0};
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assign ShiftVal = FOpCtrlE[1] ? {{64-2{1'b0}}, XManE} : {PosInt, 52'b0};
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// if shift = -1 then shift one bit right for gaurd bit (right shifting twice never rounds)
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// if the shift is negitive add a bit for sticky bit calculation
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// otherwise shift left
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assign ShiftedManTmp = &ShiftCnt ? {{64-1{1'b0}}, XAssumed1E, XFracE[51:1]} : ShiftCnt[12] ? {{64+51{1'b0}}, ~XZeroE} : ShiftVal << ShiftCnt;
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assign ShiftedManTmp = &ShiftCnt ? {{64-1{1'b0}}, XManE[52:1]} : ShiftCnt[12] ? {{64+51{1'b0}}, ~XZeroE} : ShiftVal << ShiftCnt;
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// truncate the shifted mantissa
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assign ShiftedMan = ShiftedManTmp[64+51:50];
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@ -121,7 +121,7 @@ module fcvt (
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// calculate sticky bit
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// - take into account the possible right shift from before
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// - the sticky bit calculation covers three diffrent sizes depending on the opperation
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assign Sticky = |ShiftedManTmp[49:0] | &ShiftCnt&XFracE[0] | (FOpCtrlE[0]&|ShiftedManTmp[62:50]) | (FOpCtrlE[0]&~FmtE&|ShiftedManTmp[91:63]);
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assign Sticky = |ShiftedManTmp[49:0] | &ShiftCnt&XManE[0] | (FOpCtrlE[0]&|ShiftedManTmp[62:50]) | (FOpCtrlE[0]&~FmtE&|ShiftedManTmp[91:63]);
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// determine guard, round, and least significant bit of the result
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@ -35,11 +35,10 @@ module fma(
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic XSgnE, YSgnE, ZSgnE,
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input logic [`NE-1:0] XExpE, YExpE, ZExpE,
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input logic [`NF-1:0] XFracE, YFracE, ZFracE,
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input logic [`NF:0] XManE, YManE, ZManE,
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input logic XSgnM, YSgnM, ZSgnM,
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input logic [`NE-1:0] XExpM, YExpM, ZExpM,
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input logic [`NF-1:0] XFracM, YFracM, ZFracM,
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input logic XAssumed1E, YAssumed1E, ZAssumed1E,
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input logic [`NE-1:0] XExpM, YExpM, ZExpM, // ***needed
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input logic [`NF:0] XManM, YManM, ZManM,
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input logic XDenormE, YDenormE, ZDenormE,
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input logic XZeroE, YZeroE, ZZeroE,
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input logic XNaNM, YNaNM, ZNaNM,
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@ -57,8 +56,8 @@ module fma(
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logic AddendStickyE, AddendStickyM;
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logic KillProdE, KillProdM;
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fma1 fma1 (.XExpE, .YExpE, .ZExpE, .XFracE, .YFracE, .ZFracE,
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.BiasE, .XAssumed1E, .YAssumed1E, .ZAssumed1E, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
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fma1 fma1 (.XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
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.BiasE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
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.FOpCtrlE, .FmtE, .ProdManE, .AlignedAddendE,
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.ProdExpE, .AddendStickyE, .KillProdE);
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@ -69,7 +68,7 @@ module fma(
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{AddendStickyE, KillProdE},
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{AddendStickyM, KillProdM});
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fma2 fma2(.XSgnM, .YSgnM, .ZSgnM, .XExpM, .YExpM, .ZExpM, .XFracM, .YFracM, .ZFracM,
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fma2 fma2(.XSgnM, .YSgnM, .ZSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM,
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.FOpCtrlM, .FrmM, .FmtM,
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.ProdManM, .AlignedAddendM, .ProdExpM, .AddendStickyM, .KillProdM,
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.XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM,
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@ -82,8 +81,7 @@ endmodule
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module fma1(
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// input logic XSgnE, YSgnE, ZSgnE,
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input logic [`NE-1:0] XExpE, YExpE, ZExpE, // biased exponents in B(NE.0) format
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input logic [`NF-1:0] XFracE, YFracE, ZFracE, // fractions in U(0.NF) format]
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input logic XAssumed1E, YAssumed1E, ZAssumed1E,
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input logic [`NF:0] XManE, YManE, ZManE, // fractions in U(0.NF) format]
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input logic XDenormE, YDenormE, ZDenormE,
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input logic XZeroE, YZeroE, ZZeroE,
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input logic [`NE-1:0] BiasE,
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@ -99,7 +97,7 @@ module fma1(
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logic [`NE+1:0] AlignCnt; // how far to shift the addend to align with the product in Q(NE+2.0) format *** is this enough bits?
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logic [4*`NF+5:0] ZManShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
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logic [4*`NF+5:0] ZManPreShifted; // input to the alignment shifter U(NF+5.3NF+1)
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///////////////////////////////////////////////////////////////////////////////
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// Calculate the product
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// - When multipliying two fp numbers, add the exponents
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@ -114,8 +112,8 @@ module fma1(
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// verilator lint_on WIDTH
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// Calculate the product's mantissa
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// - Add the assumed one. If the number is denormalized or zero, it does not have an assumed one.
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assign ProdManE = {XAssumed1E, XFracE} * {YAssumed1E, YFracE};
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// - Mantissa includes the assumed one. If the number is denormalized or zero, it does not have an assumed one.
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assign ProdManE = XManE * YManE;
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///////////////////////////////////////////////////////////////////////////////
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// Alignment shifter
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@ -133,7 +131,7 @@ module fma1(
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// |1'b0| addnend |
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// the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...)
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assign ZManPreShifted = {(`NF+3)'(0), {ZAssumed1E, ZFracE}, /*106*/(2*`NF+2)'(0)};
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assign ZManPreShifted = {(`NF+3)'(0), ZManE, /*106*/(2*`NF+2)'(0)};
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always_comb
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begin
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@ -143,7 +141,7 @@ module fma1(
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// | addnend |
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if ($signed(AlignCnt) <= $signed(-(`NF+4))) begin
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KillProdE = 1;
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ZManShifted = ZManPreShifted;//{107'b0, {~ZAssumed1E, ZFrac}, 54'b0};
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ZManShifted = ZManPreShifted;//{107'b0, XManE, 54'b0};
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AddendStickyE = ~(XZeroE|YZeroE);
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// If the Addend is shifted left (negitive AlignCnt)
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@ -185,7 +183,7 @@ module fma2(
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input logic XSgnM, YSgnM, ZSgnM,
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input logic [`NE-1:0] XExpM, YExpM, ZExpM,
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input logic [`NF-1:0] XFracM, YFracM, ZFracM,
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input logic [`NF:0] XManM, YManM, ZManM,
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic [2:0] FOpCtrlM, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
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input logic FmtM, // precision 1 = double 0 = single
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@ -202,7 +200,6 @@ module fma2(
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output logic [4:0] FMAFlgM); // FMA flags {invalid, divide by zero, overflow, underflow, inexact}
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logic [`NF-1:0] ResultFrac; // Result fraction
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logic [`NE-1:0] ResultExp; // Result exponent
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logic ResultSgn; // Result sign
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@ -239,11 +236,12 @@ module fma2(
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logic SigNaN; // is an input a signaling NaN
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logic UnderflowFlag; // Underflow singal used in FMAFlgM (used to avoid a circular depencency)
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logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
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logic ZSgnEffM;
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// Calculate the product's sign
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// Negate product's sign if FNMADD or FNMSUB
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assign PSgn = XSgnM ^ YSgnM ^ FOpCtrlM[1];
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@ -255,7 +253,8 @@ module fma2(
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// Negate Z when doing one of the following opperations:
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// -prod + Z
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// prod - Z
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assign InvZ = ZSgnM ^ PSgn;
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assign ZSgnEffM = ZSgnM^FOpCtrlM[0]; // Swap sign of Z for subtract
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assign InvZ = ZSgnEffM ^ PSgn;
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// Choose an inverted or non-inverted addend - the one is added later
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assign AlignedAddend2 = InvZ ? ~{1'b0, AlignedAddendM} : {1'b0, AlignedAddendM};
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@ -307,7 +306,8 @@ module fma2(
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assign SumZero = ~(|Sum);
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// determine the length of the fraction based on precision
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assign FracLen = FmtM ? `NF : 13'd23;
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//assign FracLen = FmtM ? `NF : 13'd23;
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assign FracLen = `NF;
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// Determine if the result is denormal
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assign SumExpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCnt} - (`NF+4));
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@ -374,7 +374,7 @@ module fma2(
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assign UfLSBNormSum = FmtM ? NormSum[2] : NormSum[31];
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// Deterimine if a small number was supposed to be subtrated
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assign SubBySmallNum = AddendStickyM&InvZ&~(NormSumSticky)&~ZZeroM;
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assign SubBySmallNum = AddendStickyM & InvZ & ~(NormSumSticky) & ~ZZeroM;
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always_comb begin
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// Determine if you add 1
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@ -435,13 +435,13 @@ module fma2(
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// Determine the sign if the sum is zero
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// if cancelation then 0 unless round to -infinity
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// otherwise psign
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assign ZeroSgn = (PSgn^ZSgnM)&~Underflow ? FrmM == 3'b010 : PSgn;
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assign ZeroSgn = (PSgn^ZSgnEffM)&~Underflow ? FrmM == 3'b010 : PSgn;
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign ResultSgnTmp = InvZ&(ZSgnM)&NegSum | InvZ&PSgn&~NegSum | ((ZSgnM)&PSgn);
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assign ResultSgnTmp = InvZ&(ZSgnEffM)&NegSum | InvZ&PSgn&~NegSum | ((ZSgnEffM)&PSgn);
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assign ResultSgn = SumZero ? ZeroSgn : ResultSgnTmp;
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@ -460,7 +460,7 @@ module fma2(
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// 3) 0 * Inf
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assign MaxExp = FmtM ? {`NE{1'b1}} : 13'd255;
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assign SigNaN = XSNaNM | YSNaNM | ZSNaNM;
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assign Invalid = SigNaN | ((XInfM || YInfM) & ZInfM & (PSgn ^ ZSgnM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM);
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assign Invalid = SigNaN | ((XInfM || YInfM) & ZInfM & (PSgn ^ ZSgnEffM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM);
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// Set Overflow flag if the number is too big to be represented
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// - Don't set the overflow flag if an overflowed result isn't outputed
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@ -490,29 +490,29 @@ module fma2(
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///////////////////////////////////////////////////////////////////////////////
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// Select the result
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///////////////////////////////////////////////////////////////////////////////
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assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XFracM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XFracM[50:29]};
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assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YFracM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YFracM[50:29]};
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assign ZNaNResult = FmtM ? {ZSgnM, ZExpM, 1'b1, ZFracM[`NF-2:0]} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], 1'b1, ZFracM[50:29]};
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assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]};
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assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]};
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assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]};
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assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} :
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{ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :
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((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} :
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{{32{1'b1}}, ResultSgn, 8'hff, 23'b0};
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assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
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assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZFracM} - (Minus1&AddendStickyM) + (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[7:0], ZFracM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
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assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} - (Minus1&AddendStickyM) + (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[7:0], ZManM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
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assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + (CalcPlus1&(AddendStickyM|FrmM[1])) : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}};
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assign FMAResM = XNaNM ? XNaNResult :
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YNaNM ? YNaNResult :
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ZNaNM ? ZNaNResult :
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Invalid ? InvalidResult : // has to be before inf
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XInfM ? FmtM ? {PSgn, XExpM, XFracM} : {{32{1'b1}}, PSgn, XExpM[7:0], XFracM[51:29]} :
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YInfM ? FmtM ? {PSgn, YExpM, YFracM} : {{32{1'b1}}, PSgn, YExpM[7:0], YFracM[51:29]} :
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ZInfM ? FmtM ? {ZSgnM, ZExpM, ZFracM} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], ZFracM[51:29]} :
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XInfM ? FmtM ? {PSgn, XExpM, XManM[`NF-1:0]} : {{32{1'b1}}, PSgn, XExpM[7:0], XManM[51:29]} :
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YInfM ? FmtM ? {PSgn, YExpM, YManM[`NF-1:0]} : {{32{1'b1}}, PSgn, YExpM[7:0], YManM[51:29]} :
|
||||
ZInfM ? FmtM ? {ZSgnEffM, ZExpM, ZManM[`NF-1:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], ZManM[51:29]} :
|
||||
Overflow ? OverflowResult :
|
||||
KillProdM ? KillProdResult : // has to be after Underflow
|
||||
Underflow & ~ResultDenorm ? UnderflowResult :
|
||||
FmtM ? {ResultSgn, ResultExp, ResultFrac} :
|
||||
{{32{1'b1}}, ResultSgn, ResultExp[7:0], ResultFrac[51:29]};
|
||||
|
||||
|
||||
// *** use NF where needed
|
||||
|
||||
endmodule
|
||||
@ -68,13 +68,12 @@ module fpu (
|
||||
logic [`XLEN-1:0] FSrcXMAligned;
|
||||
logic [63:0] FSrcXE, FSrcXM; // Input 1 to the various units (after forwarding)
|
||||
logic [63:0] FSrcYE; // Input 2 to the various units (after forwarding)
|
||||
logic [63:0] FSrcZE; // Input 3 to the various units (after forwarding)
|
||||
logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
|
||||
|
||||
// unpacking signals
|
||||
logic XSgnE, YSgnE, ZSgnE;
|
||||
logic [10:0] XExpE, YExpE, ZExpE;
|
||||
logic [51:0] XFracE, YFracE, ZFracE;
|
||||
logic XAssumed1E, YAssumed1E, ZAssumed1E;
|
||||
logic [52:0] XManE, YManE, ZManE;
|
||||
logic XNaNE, YNaNE, ZNaNE;
|
||||
logic XSNaNE, YSNaNE, ZSNaNE;
|
||||
logic XDenormE, YDenormE, ZDenormE;
|
||||
@ -86,7 +85,7 @@ module fpu (
|
||||
|
||||
logic XSgnM, YSgnM, ZSgnM;
|
||||
logic [10:0] XExpM, YExpM, ZExpM;
|
||||
logic [51:0] XFracM, YFracM, ZFracM;
|
||||
logic [52:0] XManM, YManM, ZManM;
|
||||
logic XNaNM, YNaNM, ZNaNM;
|
||||
logic XSNaNM, YSNaNM, ZSNaNM;
|
||||
logic XZeroM, YZeroM, ZZeroM;
|
||||
@ -162,25 +161,26 @@ module fpu (
|
||||
// Hazard unit for FPU
|
||||
fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResultSelM, .FStallD,
|
||||
.FForwardXE, .FForwardYE, .FForwardZE);
|
||||
|
||||
|
||||
// forwarding muxs
|
||||
mux3 #(64) fxemux(FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE);
|
||||
mux3 #(64) fyemux(FRD2E, FPUResultW, FResM, FForwardYE, FSrcYE);
|
||||
mux3 #(64) fzemux(FRD3E, FPUResultW, FResM, FForwardZE, FSrcZE);
|
||||
|
||||
mux3 #(64) fzemux(FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE);
|
||||
mux2 #(64) fzmulmux(FPreSrcZE, 64'b0, FOpCtrlE[2], FSrcZE); // Force Z to be 0 for multiply instructions
|
||||
|
||||
unpacking unpacking(.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE),
|
||||
.FOpCtrlE(FOpCtrlE[2:0]), .FmtE, .XSgnE, .YSgnE,
|
||||
.ZSgnE, .XExpE, .YExpE, .ZExpE, .XFracE, .YFracE, .ZFracE,
|
||||
.XAssumed1E, .YAssumed1E, .ZAssumed1E, .XNaNE, .YNaNE, .ZNaNE,
|
||||
.ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
|
||||
.XNaNE, .YNaNE, .ZNaNE,
|
||||
.XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
|
||||
.XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
|
||||
// first of two-stage instance of floating-point fused multiply-add unit
|
||||
fma fma (.clk, .reset, .FlushM, .StallM,
|
||||
.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XFracE, .YFracE, .
|
||||
ZFracE, .XAssumed1E, .YAssumed1E, .ZAssumed1E, .XDenormE, .YDenormE,
|
||||
.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .
|
||||
ZManE, .XDenormE, .YDenormE,
|
||||
.ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE,
|
||||
.XSgnM, .YSgnM, .ZSgnM, .XExpM, .YExpM, .ZExpM, .XFracM,
|
||||
.YFracM, .ZFracM, .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
|
||||
.XSgnM, .YSgnM, .ZSgnM, .XExpM, .YExpM, .ZExpM, .XManM,
|
||||
.YManM, .ZManM, .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
|
||||
// .FSrcXE, .FSrcYE, .FSrcZE, .FSrcXM, .FSrcYM, .FSrcZM,
|
||||
.FOpCtrlE(FOpCtrlE[2:0]), .FOpCtrlM(FOpCtrlM[2:0]),
|
||||
.FmtE, .FmtM, .FrmM, .FMAFlgM, .FMAResM);
|
||||
@ -216,17 +216,17 @@ module fpu (
|
||||
.FSrcXE, .FSrcYE, .FOpCtrlE, .FAddResM, .FAddFlgM);
|
||||
|
||||
// first and only instance of floating-point comparator
|
||||
fcmp fcmp (.op1({XSgnE,XExpE,XFracE}), .op2({YSgnE,YExpE,YFracE}), .FSrcXE,
|
||||
fcmp fcmp (.op1({XSgnE,XExpE,XManE[`NF-1:0]}), .op2({YSgnE,YExpE,YManE[`NF-1:0]}), .FSrcXE,
|
||||
.FSrcYE, .FOpCtrlE(FOpCtrlE[2:0]), .FmtE,
|
||||
.Invalid(CmpNVE), .CmpResE, .XNaNE, .YNaNE, .XZeroE, .YZeroE);
|
||||
|
||||
// first and only instance of floating-point sign converter
|
||||
fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .XExpE, .XFracE, .FmtE, .SgnResE, .SgnNVE, .XExpMaxE);
|
||||
|
||||
fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE, .SgnNVE, .XExpMaxE);
|
||||
|
||||
// first and only instance of floating-point classify unit
|
||||
fclassify fclassify (.XSgnE, .XFracE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE);
|
||||
fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE);
|
||||
|
||||
fcvt fcvt (.XSgnE, .XExpE, .XFracE, .XAssumed1E, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .SrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE);
|
||||
fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .SrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE);
|
||||
|
||||
// output for store instructions
|
||||
assign FWriteDataE = FSrcYE[`XLEN-1:0];
|
||||
@ -237,9 +237,9 @@ module fpu (
|
||||
flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM);
|
||||
// flopenrc #(64) EMFpReg2(clk, reset, FlushM, ~StallM, FSrcYE, FSrcYM);
|
||||
// flopenrc #(64) EMFpReg3(clk, reset, FlushM, ~StallM, FSrcZE, FSrcZM);
|
||||
flopenrc #(64) EMFpReg4(clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XFracE}, {XSgnM,XExpM,XFracM});
|
||||
flopenrc #(64) EMFpReg5(clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YFracE}, {YSgnM,YExpM,YFracM});
|
||||
flopenrc #(64) EMFpReg6(clk, reset, FlushM, ~StallM, {ZSgnE,ZExpE,ZFracE}, {ZSgnM,ZExpM,ZFracM});
|
||||
flopenrc #(65) EMFpReg4(clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM});
|
||||
flopenrc #(65) EMFpReg5(clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM});
|
||||
flopenrc #(65) EMFpReg6(clk, reset, FlushM, ~StallM, {ZSgnE,ZExpE,ZManE}, {ZSgnM,ZExpM,ZManM});
|
||||
flopenrc #(12) EMFpReg7(clk, reset, FlushM, ~StallM,
|
||||
{XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
|
||||
{XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});
|
||||
|
||||
@ -2,8 +2,7 @@
|
||||
|
||||
module fsgn (
|
||||
input logic XSgnE, YSgnE,
|
||||
input logic [10:0] XExpE,
|
||||
input logic [51:0] XFracE,
|
||||
input logic [63:0] FSrcXE,
|
||||
input logic XExpMaxE,
|
||||
input logic FmtE,
|
||||
input logic [1:0] SgnOpCodeE,
|
||||
@ -21,7 +20,7 @@ module fsgn (
|
||||
//
|
||||
|
||||
assign ResSgn = SgnOpCodeE[1] ? (XSgnE ^ YSgnE) : (YSgnE ^ SgnOpCodeE[0]);
|
||||
assign SgnResE = FmtE ? {ResSgn, XExpE, XFracE} : {{32{1'b1}}, ResSgn, XExpE[7:0], XFracE[51:29]};
|
||||
assign SgnResE = FmtE ? {ResSgn, FSrcXE[62:0]} : {FSrcXE[63:32], ResSgn, FSrcXE[30:0]};
|
||||
|
||||
//If the exponent is all ones, then the value is either Inf or NaN,
|
||||
//both of which will produce a QNaN/SNaN value of some sort. This will
|
||||
|
||||
@ -4,8 +4,7 @@ module unpacking (
|
||||
input logic [2:0] FOpCtrlE,
|
||||
output logic XSgnE, YSgnE, ZSgnE,
|
||||
output logic [10:0] XExpE, YExpE, ZExpE,
|
||||
output logic [51:0] XFracE, YFracE, ZFracE,
|
||||
output logic XAssumed1E, YAssumed1E, ZAssumed1E,
|
||||
output logic [52:0] XManE, YManE, ZManE,
|
||||
output logic XNormE,
|
||||
output logic XNaNE, YNaNE, ZNaNE,
|
||||
output logic XSNaNE, YSNaNE, ZSNaNE,
|
||||
@ -15,41 +14,48 @@ module unpacking (
|
||||
output logic XInfE, YInfE, ZInfE,
|
||||
output logic XExpMaxE
|
||||
);
|
||||
//***rename to make significand = 1.frac m = significand
|
||||
|
||||
logic [51:0] XFracE, YFracE, ZFracE;
|
||||
logic XExpNonzero, YExpNonzero, ZExpNonzero;
|
||||
logic XFracZero, YFracZero, ZFracZero; // input fraction zero
|
||||
logic XExpZero, YExpZero, ZExpZero; // input exponent zero
|
||||
logic [63:0] Addend; // value to add (Z or zero)
|
||||
logic YExpMaxE, ZExpMaxE; // input exponent all 1s
|
||||
|
||||
assign Addend = FOpCtrlE[2] ? 64'b0 : Z; // Z is only used in the FMA, and is set to Zero if a multiply opperation
|
||||
assign XSgnE = FmtE ? X[63] : X[31];
|
||||
assign YSgnE = FmtE ? Y[63] : Y[31];
|
||||
assign ZSgnE = FmtE ? Addend[63]^FOpCtrlE[0] : Addend[31]^FOpCtrlE[0];
|
||||
assign ZSgnE = FmtE ? Z[63] : Z[31];
|
||||
|
||||
assign XExpE = FmtE ? X[62:52] : {3'b0, X[30:23]};
|
||||
assign XExpE = FmtE ? X[62:52] : {X[30], {3{~X[30]&~XExpZero|XExpMaxE}}, X[29:23]};
|
||||
assign YExpE = FmtE ? Y[62:52] : {Y[30], {3{~Y[30]&~YExpZero|YExpMaxE}}, Y[29:23]};
|
||||
assign ZExpE = FmtE ? Z[62:52] : {Z[30], {3{~Z[30]&~ZExpZero|ZExpMaxE}}, Z[29:23]};
|
||||
/* assign XExpE = FmtE ? X[62:52] : {3'b0, X[30:23]}; // *** maybe convert to full number of bits here?
|
||||
assign YExpE = FmtE ? Y[62:52] : {3'b0, Y[30:23]};
|
||||
assign ZExpE = FmtE ? Addend[62:52] : {3'b0, Addend[30:23]};
|
||||
assign ZExpE = FmtE ? Z[62:52] : {3'b0, Z[30:23]};*/
|
||||
|
||||
assign XFracE = FmtE ? X[51:0] : {X[22:0], 29'b0};
|
||||
assign YFracE = FmtE ? Y[51:0] : {Y[22:0], 29'b0};
|
||||
assign ZFracE = FmtE ? Addend[51:0] : {Addend[22:0], 29'b0};
|
||||
assign ZFracE = FmtE ? Z[51:0] : {Z[22:0], 29'b0};
|
||||
|
||||
assign XAssumed1E = |XExpE;
|
||||
assign YAssumed1E = |YExpE;
|
||||
assign ZAssumed1E = |ZExpE;
|
||||
assign XExpNonzero = FmtE ? |X[62:52] : |X[30:23];
|
||||
assign YExpNonzero = FmtE ? |Y[62:52] : |Y[30:23];
|
||||
assign ZExpNonzero = FmtE ? |Z[62:52] : |Z[30:23];
|
||||
|
||||
assign XExpZero = ~XAssumed1E;
|
||||
assign YExpZero = ~YAssumed1E;
|
||||
assign ZExpZero = ~ZAssumed1E;
|
||||
assign XManE = {XExpNonzero, XFracE};
|
||||
assign YManE = {YExpNonzero, YFracE};
|
||||
assign ZManE = {ZExpNonzero, ZFracE};
|
||||
|
||||
assign XExpZero = ~XExpNonzero;
|
||||
assign YExpZero = ~YExpNonzero;
|
||||
assign ZExpZero = ~ZExpNonzero;
|
||||
|
||||
assign XFracZero = ~|XFracE;
|
||||
assign YFracZero = ~|YFracE;
|
||||
assign ZFracZero = ~|ZFracE;
|
||||
|
||||
assign XExpMaxE = FmtE ? &XExpE[10:0] : &XExpE[7:0];
|
||||
assign YExpMaxE = FmtE ? &YExpE[10:0] : &YExpE[7:0];
|
||||
assign ZExpMaxE = FmtE ? &ZExpE[10:0] : &ZExpE[7:0];
|
||||
|
||||
assign XExpMaxE = FmtE ? &X[62:52] : &X[30:23];
|
||||
assign YExpMaxE = FmtE ? &Y[62:52] : &Y[30:23];
|
||||
assign ZExpMaxE = FmtE ? &Z[62:52] : &Z[30:23];
|
||||
|
||||
assign XNormE = ~(XExpMaxE|XExpZero);
|
||||
|
||||
assign XNaNE = XExpMaxE & ~XFracZero;
|
||||
@ -72,6 +78,7 @@ module unpacking (
|
||||
assign YZeroE = YExpZero & YFracZero;
|
||||
assign ZZeroE = ZExpZero & ZFracZero;
|
||||
|
||||
assign BiasE = FmtE ? 13'h3ff : 13'h7f;
|
||||
//assign BiasE = FmtE ? 13'h3ff : 13'h7f; // *** is it better to convert to full precision exponents so bias isn't needed?
|
||||
assign BiasE = 13'h3ff; // always use 1023 because exponents are unpacked to double precision
|
||||
|
||||
endmodule
|
||||
@ -90,10 +90,10 @@ string tests32f[] = '{
|
||||
"rv64f/I-FSW-01", "2000",
|
||||
"rv64f/I-FCLASS-S-01", "2000",
|
||||
"rv64f/I-FADD-S-01", "2000",
|
||||
"rv64f/I-FCVT-S-L-01", "2000",
|
||||
"rv64f/I-FCVT-S-LU-01", "2000",
|
||||
"rv64f/I-FCVT-S-W-01", "2000",
|
||||
"rv64f/I-FCVT-S-WU-01", "2000",
|
||||
// "rv64f/I-FCVT-S-L-01", "2000",
|
||||
// "rv64f/I-FCVT-S-LU-01", "2000",
|
||||
// "rv64f/I-FCVT-S-W-01", "2000",
|
||||
// "rv64f/I-FCVT-S-WU-01", "2000",
|
||||
"rv64f/I-FCVT-L-S-01", "2000",
|
||||
"rv64f/I-FCVT-LU-S-01", "2000",
|
||||
"rv64f/I-FCVT-W-S-01", "2000",
|
||||
@ -122,16 +122,6 @@ string tests32f[] = '{
|
||||
"rv64d/I-FMV-X-D-01", "2000",
|
||||
"rv64d/I-FMV-D-X-01", "2000",
|
||||
"rv64d/I-FDIV-D-01", "2000",
|
||||
"rv64d/I-FCVT-D-L-01", "2000",
|
||||
"rv64d/I-FCVT-D-LU-01", "2000",
|
||||
"rv64d/I-FCVT-D-S-01", "2000",
|
||||
"rv64d/I-FCVT-D-W-01", "2000",
|
||||
"rv64d/I-FCVT-D-WU-01", "2000",
|
||||
"rv64d/I-FCVT-L-D-01", "2000",
|
||||
"rv64d/I-FCVT-LU-D-01", "2000",
|
||||
"rv64d/I-FCVT-S-D-01", "2000",
|
||||
"rv64d/I-FCVT-W-D-01", "2000",
|
||||
"rv64d/I-FCVT-WU-D-01", "2000",
|
||||
"rv64d/I-FNMADD-D-01", "2000",
|
||||
"rv64d/I-FNMSUB-D-01", "2000",
|
||||
"rv64d/I-FMSUB-D-01", "2000",
|
||||
@ -148,8 +138,18 @@ string tests32f[] = '{
|
||||
"rv64d/I-FSGNJN-D-01", "2000",
|
||||
"rv64d/I-FSGNJX-D-01", "2000",
|
||||
"rv64d/I-FSQRT-D-01", "2000",
|
||||
"rv64d/I-FSUB-D-01", "2000"
|
||||
};
|
||||
"rv64d/I-FSUB-D-01", "2000",
|
||||
// "rv64d/I-FCVT-D-L-01", "2000",
|
||||
// "rv64d/I-FCVT-D-LU-01", "2000",
|
||||
"rv64d/I-FCVT-D-S-01", "2000",
|
||||
// "rv64d/I-FCVT-D-W-01", "2000",
|
||||
// "rv64d/I-FCVT-D-WU-01", "2000",
|
||||
"rv64d/I-FCVT-L-D-01", "2000",
|
||||
"rv64d/I-FCVT-LU-D-01", "2000",
|
||||
"rv64d/I-FCVT-S-D-01", "2000",
|
||||
"rv64d/I-FCVT-W-D-01", "2000",
|
||||
"rv64d/I-FCVT-WU-D-01", "2000"
|
||||
};
|
||||
|
||||
string tests64a[] = '{
|
||||
//"rv64a/WALLY-AMO", "2110",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user