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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2021-07-21 16:39:07 -05:00
commit 71375ba655
3 changed files with 3 additions and 6 deletions
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3
wally-pipelined/src/mmu/tlb.sv
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@ -100,14 +100,13 @@ module tlb #(parameter TLB_ENTRIES = 8,
logic [7:0] PTEAccessBits;
logic [11:0] PageOffset;
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
logic [1:0] HitPageType;
logic CAMHit;
logic SV39Mode;
assign VPN = VAdr[`VPN_BITS+11:12];
tlbcontrol tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
.PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault,
.SV39Mode, .Translate);

2
wally-pipelined/src/mmu/tlbcamline.sv
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@ -101,6 +101,6 @@ module tlbcamline #(parameter KEY_BITS = 20,
// On a flush, zero the valid bit and leave the key unchanged.
// *** Might we want to update stored key right away to output match on the
// write cycle? (using a mux)
flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid);
flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key);
endmodule

4
wally-pipelined/src/mmu/tlbcontrol.sv
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@ -25,9 +25,7 @@
`include "wally-config.vh"
// The TLB will have 2**ENTRY_BITS total entries
module tlbcontrol #(parameter TLB_ENTRIES = 8,
parameter ITLB = 0) (
module tlbcontrol #(parameter ITLB = 0) (
// Current value of satp CSR (from privileged unit)
input logic [`SVMODE_BITS-1:0] SATP_MODE,