Ross Thompson
f6c6cb9ed2
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
Ross Thompson
b3694bfdfd
Fixed boot loader program to start at correct address.
...
modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
2021-10-11 17:22:23 -05:00
Shreya Sanghai
0acf9fd746
made redunantmul generate DW02_multp for synopsys sythnesis
2021-10-11 11:54:39 -07:00
Shreya Sanghai
84ff2b49c7
actually added redundant mul
2021-10-11 11:29:13 -07:00
David Harris
af7903e1b2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-11 11:21:39 -07:00
David Harris
1cdc5db75d
Extended lint to check rv32/64g (including fpu. Not clean yet.
2021-10-11 11:20:42 -07:00
Shreya Sanghai
a1c9ffdf2b
added redundant multiplier
2021-10-11 11:20:12 -07:00
David Harris
ab6a796690
Starting to optimize multiplier
2021-10-11 11:06:07 -07:00
Ross Thompson
f1eda1bf6f
Fixed sdc byte and nibble orders.
2021-10-11 12:15:52 -05:00
Ross Thompson
9150133c7d
Fpga simualtion files.
2021-10-11 10:24:40 -05:00
Ross Thompson
bfe633d087
Partially working sd card reader.
2021-10-11 10:23:45 -05:00
David Harris
f1190b6ceb
intdiv cleanup
2021-10-11 08:14:21 -07:00
David Harris
4139f27d10
Divider FSM simplification
2021-10-10 22:24:14 -07:00
David Harris
75c17dc372
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
James E. Stine
2b66615812
Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH
2021-10-10 15:44:01 -05:00
bbracker
13352eccda
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 13:12:44 -07:00
bbracker
161767cddd
make regression expect what buildroot is actually able to reach
2021-10-10 13:12:36 -07:00
David Harris
a6c6b2b974
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 12:26:15 -07:00
David Harris
caf3c2de9b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 12:25:11 -07:00
bbracker
90ccd60790
simplify flopenrc's that didn't actually need to be flopenrc's
2021-10-10 12:25:05 -07:00
David Harris
43d92f2507
Divider cleanup
2021-10-10 12:24:44 -07:00
David Harris
6704e37597
Simplifying divider FSM
2021-10-10 12:21:43 -07:00
David Harris
4deae8019a
Simplifying divider FSM
2021-10-10 12:21:36 -07:00
David Harris
2759f1fcb1
Moved & ~StallM from FSM into DivStartE
2021-10-10 11:49:32 -07:00
David Harris
635fe181f8
Moved divide iteration register names to M stage
2021-10-10 11:30:53 -07:00
David Harris
b713b6ca87
Simplified remainder for divide by 0
2021-10-10 11:20:07 -07:00
David Harris
6988c8c37c
divider control signal simplificaiton
2021-10-10 10:55:02 -07:00
David Harris
c2bb0324c6
Removed negedge flops from divider
2021-10-10 10:41:13 -07:00
bbracker
2f02287f91
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 10:10:06 -07:00
bbracker
a88ae5aaff
use correct string formatting function
2021-10-10 10:09:59 -07:00
David Harris
3aa9e088c8
Simplified divider sign handling
2021-10-10 08:35:26 -07:00
David Harris
39bbeefa78
renamed DivStart
2021-10-10 08:32:04 -07:00
David Harris
64ed267825
renamed DivSigned
2021-10-10 08:30:19 -07:00
Katherine Parry
77fe00947e
FMA matches diagram and lint warnings fixed
2021-10-09 17:38:10 -07:00
bbracker
6fce53d146
make testbench-linux halt on some discrepancies with QEMUw
2021-10-09 17:22:30 -07:00
kipmacsaigoren
96565f9435
rename adder in fpu for synthesis
2021-10-08 17:47:54 -05:00
kipmacsaigoren
7fde7aae6e
Merging new changes into the old one's I've made in the OKstate servers
2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
303beaa083
updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully.
2021-10-08 15:40:18 -07:00
Kip Macsai-Goren
f3058f94c6
removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.
2021-10-08 15:33:18 -07:00
kipmacsaigoren
2d4623b49c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-08 12:01:44 -05:00
David Harris
3d0383c154
moved fp vectors into vectors subdirectory
2021-10-07 23:28:06 -04:00
David Harris
6dd85b80a2
Included TestFloat and SoftFloat
2021-10-07 23:03:45 -04:00
bbracker
55f6584e62
update wave-do
2021-10-07 19:16:52 -04:00
bbracker
1824b2af13
fix div restarting bug
2021-10-07 18:55:00 -04:00
James E. Stine
28e147bb19
update scripts
2021-10-07 15:14:54 -05:00
bbracker
91d9b6800b
update linker scripts to look for vmlinux files
2021-10-06 16:55:38 -04:00
James E. Stine
8429078d4f
TV for conversion and compare
2021-10-06 14:38:32 -05:00
James E. Stine
199ce88b39
Add generic wave command file
2021-10-06 13:17:49 -05:00
James E. Stine
93668b5185
Update to testbench for FP stuff
2021-10-06 13:16:38 -05:00
kipmacsaigoren
8db7ce002d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-06 11:52:34 -05:00