kipmacsaigoren 8db7ce002d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2021-10-06 11:52:34 -05:00
..
bin	Added testbench-arch for riscv-arch-test suite	2021-09-08 15:59:40 -04:00
config	Reduced cycle count for DIVW/DIVUW by two	2021-10-03 09:42:22 -04:00
fpu-testfloat/FMA/tbgen	FMA cleanup	2021-08-28 10:53:35 -04:00
linux-testgen	checkpoint generator bugfixes	2021-10-03 00:30:04 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Replacing XE and DE with SrcAE and SrcBE in divider	2021-10-03 11:11:53 -04:00
src	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-06 11:52:34 -05:00
testbench	Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included	2021-10-06 08:56:01 -05:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00