Ross Thompson
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050523487c
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Changed names of lsu address signals.
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2021-12-29 15:03:34 -06:00 |
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Ross Thompson
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50b307bc0e
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Looks like rdtime was accidentally replaced with rrame from a find and replace.
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2021-12-20 21:26:38 -06:00 |
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David Harris
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a25d541dcf
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Moved generate of conditional units to hart
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2021-12-19 17:03:57 -08:00 |
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David Harris
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3c3bfd055e
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Moved generate statements for optional units into wallypipelinedhart
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2021-12-19 16:53:41 -08:00 |
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Ross Thompson
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d9cc9afd49
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Changes to buildroot to support MemAdrM to IEUAdrM name changes.
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2021-12-19 18:24:40 -06:00 |
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David Harris
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aebd746e71
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Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
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2021-12-15 12:10:45 -08:00 |
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David Harris
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865d5ce0b1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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bbracker
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5feccaec68
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fix release of ReadDataM
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2021-12-08 14:11:43 -08:00 |
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bbracker
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979580b1e7
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fix checkpointing so that it can find the synchronized reset signal
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2021-12-07 13:12:06 -08:00 |
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Skylar Litz
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546f7fb4c2
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fix some interrupt timing bugs
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2021-12-03 12:32:38 -08:00 |
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Ross Thompson
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500e6ff430
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Fixed buildroot to work with the fpga's merge.
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2021-12-02 18:09:43 -06:00 |
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Ross Thompson
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a871118116
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Merge branch 'main' into fpga
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2021-11-29 10:10:37 -06:00 |
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Ross Thompson
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5642918ead
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Merge branch 'main' into fpga
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2021-11-29 10:06:53 -06:00 |
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bbracker
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fed0bb08d6
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UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
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2021-11-25 11:01:59 -08:00 |
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bbracker
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cffb72042a
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activate STVAL for buildroot
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2021-11-21 10:40:28 -08:00 |
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Skylar Litz
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6fde97b16c
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fixed interrupt timing bug
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2021-11-16 16:46:17 -08:00 |
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bbracker
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2203590f9f
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get current privilege level from GDB for checkpoints
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2021-11-15 14:49:00 -08:00 |
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Skylar Litz
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3dd83b3113
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fix timing of delayed interrupt
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2021-11-11 09:35:51 -08:00 |
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bbracker
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c92d41a597
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checkpoint MIDELEG support
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2021-11-06 03:44:23 -07:00 |
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bbracker
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bc6332a780
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fix merge conflict
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2021-11-05 23:42:15 -07:00 |
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bbracker
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17e776f853
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checkpoints now use binary ram files
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2021-11-05 22:37:05 -07:00 |
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bbracker
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0c7681b942
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fix testbench interrupt timing
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2021-11-02 21:19:12 -07:00 |
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bbracker
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66e53929ce
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adapt testbench linux to use reset_ext
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2021-10-25 13:26:44 -07:00 |
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bbracker
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8c4e6baf48
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change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
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2021-10-25 12:25:32 -07:00 |
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bbracker
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9b98a499d7
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some linux testbench cleanup
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2021-10-25 10:04:30 -07:00 |
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bbracker
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046a78a8fc
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manually resolved git merge conflicts in testbench linux after checkpointing
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2021-10-24 15:02:19 -07:00 |
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bbracker
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36b39358c6
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add checkpointing to linux testbench
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2021-10-24 06:47:35 -07:00 |
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bbracker
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26eead1c77
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add W stage signals to linux testbench
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2021-10-23 14:00:53 -07:00 |
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bbracker
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3c0b0987d2
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add option for regression to do a partial execution of buildroot
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2021-10-23 13:17:30 -07:00 |
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Ross Thompson
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de4ea16d32
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Merge branch 'main' into fpga
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2021-10-20 16:24:55 -05:00 |
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bbracker
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4abc6fc915
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change infrastructure to expect only 6.3 million from buildroot
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2021-10-12 10:41:15 -07:00 |
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Ross Thompson
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f6c6cb9ed2
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Merge branch 'main' into fpga
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2021-10-11 18:17:58 -05:00 |
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bbracker
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a88ae5aaff
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use correct string formatting function
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2021-10-10 10:09:59 -07:00 |
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bbracker
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6fce53d146
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make testbench-linux halt on some discrepancies with QEMUw
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2021-10-09 17:22:30 -07:00 |
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Skylar Litz
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5bcae393c9
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added delayed MIP signal
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2021-10-04 18:23:31 -04:00 |
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bbracker
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6aa79657ed
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Revert "first attempt at verilog side of checkpoint functionality"
This reverts commit fec96218f6.
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2021-09-30 20:45:26 -04:00 |
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bbracker
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fec96218f6
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first attempt at verilog side of checkpoint functionality
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2021-09-28 23:17:58 -04:00 |
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bbracker
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7117c0493c
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condense testbench code; debug_level of 0 means don't check at all
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2021-09-27 03:03:11 -04:00 |
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Ross Thompson
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4d1b02c068
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Merge branch 'main' into fpga
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2021-09-26 13:22:53 -05:00 |
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Ross Thompson
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4f7bc1be48
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Added either the sdModel or constant driver for the SDC ports in all test benches.
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2021-09-24 12:31:51 -05:00 |
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bbracker
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3f96ff0ac0
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switch testbench-linux's interrupts from xcause to mip and improve warning messages
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2021-09-22 12:33:11 -04:00 |
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bbracker
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ff5379fd95
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fix regression
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2021-09-15 17:30:59 -04:00 |
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Ross Thompson
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6550f38af9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-09-08 12:47:03 -05:00 |
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bbracker
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bb84354a47
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fixed bug where M mode was sensitive to S mode traps
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2021-09-07 19:14:39 -04:00 |
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bbracker
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f8272c45d1
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make testbench successfully deactivate TimerIntM so as to create a nice pulse
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2021-09-07 15:36:47 -04:00 |
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bbracker
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da9a366d20
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No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
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2021-09-06 22:59:54 -04:00 |
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bbracker
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b3bc3cf6d0
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modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations)
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2021-09-04 19:49:26 -04:00 |
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Ross Thompson
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86fc632790
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Moved data path logic from icacheCntrl to icache.
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2021-08-26 10:58:19 -05:00 |
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Ross Thompson
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fe378f2692
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Added function tracking to linux test bench.
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2021-08-24 11:08:46 -05:00 |
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Ross Thompson
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c31b7b4dc5
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Wally previously was overcounting retired instructions when they were flushed.
InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
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2021-08-23 12:24:03 -05:00 |
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