Ross Thompson
736a30afac
Missing a file. Last commit will fail.
2022-11-17 17:45:41 -06:00
Ross Thompson
4fbda554ee
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-17 17:38:52 -06:00
Ross Thompson
a1f39a8186
Finally have the correct replacement policy implementation.
2022-11-17 17:36:37 -06:00
Ross Thompson
8692bafd04
Updated fpga wave configuration.
2022-11-16 15:57:19 -06:00
Ross Thompson
b108e0a594
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-16 15:39:17 -06:00
Ross Thompson
ac0f6ddb7b
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
2022-11-16 15:38:37 -06:00
Ross Thompson
9b2236b2a0
Progress on the cache replacement policy implementation.
2022-11-16 15:35:34 -06:00
Ross Thompson
d1ce84d172
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-16 12:44:06 -06:00
Ross Thompson
cf964e30fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-16 12:42:29 -06:00
Ross Thompson
5f7b0b8a9b
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
2022-11-16 12:36:58 -06:00
David Harris
bc3b783543
comment cleanup
2022-11-16 10:23:20 -08:00
David Harris
ddba68605e
Renamed DivBusy to FDivBusyE in FPU
2022-11-16 10:13:27 -08:00
David Harris
e008d663f4
Moved DivStartE to fdivsqrtfsm
2022-11-16 10:00:07 -08:00
Ross Thompson
900a326a23
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
2022-11-16 11:15:34 -06:00
Ross Thompson
3fbacc2339
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-15 14:49:32 -06:00
cturek
6fe35ee0e3
Attempt to fix FPGA synth errors
2022-11-15 20:34:28 +00:00
cturek
1c49d4a1c2
Fixed lint errors in postprocessing
2022-11-15 20:31:23 +00:00
Ross Thompson
3de5144ae4
Updated vcu118 constraints to run cpu at 38.43Mhz.
2022-11-15 10:19:38 -06:00
Ross Thompson
4b5ec21ef4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-15 10:18:56 -06:00
Ross Thompson
ec6517fadd
Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
2022-11-14 16:02:20 -06:00
Ross Thompson
f03d5d3ac8
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
1bf838fa6b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 13:48:56 -06:00
David Harris
895ee3d773
Removed comment about nonexistent possible bug
2022-11-14 09:56:33 -08:00
David Harris
cae3e00751
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 09:52:24 -08:00
David Harris
79d416537a
Removed comment about nonexistent possible bug
2022-11-14 09:52:21 -08:00
Ross Thompson
1a00e7bbee
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
5800dfde60
Updated wave file.
2022-11-13 21:34:45 -06:00
cturek
0b2c8b9d46
Added majority of combinational logic
2022-11-14 00:06:38 +00:00
cturek
74f58b5d89
Added Quotient/Remainder calcs to normal termination
2022-11-13 23:44:34 +00:00
cturek
b3bfdbad18
Added flops for n and m, added B=0 signal
2022-11-13 23:02:43 +00:00
cturek
9c70ab917c
Added A<B signal to fdivsqrt, started postprocessing merge
2022-11-13 22:40:26 +00:00
Ross Thompson
a27b81ef90
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
3ac6514856
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
0ce3cc393a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-13 04:23:26 -08:00
David Harris
157f816cd3
HPTW cleanup
2022-11-13 04:23:23 -08:00
David Harris
0502b8ea4d
Comments about division hazards
2022-11-13 04:17:37 -08:00
Ross Thompson
b812549f38
Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
...
Increased CPU clock speed from 30 Mhz to 35 Mhz.
2022-11-11 15:33:03 -06:00
Ross Thompson
90697ef888
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
cturek
ff410cd849
Added integer step counter to fsm
2022-11-11 00:23:25 +00:00
Ross Thompson
c2e3bad3f5
Fixed name change in hptw.
2022-11-10 16:13:31 -06:00
Ross Thompson
7311eca5ff
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
64b818c49a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
31d5eabd77
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
3653d6b3ed
Renamed CACHE_EVICT to CACHE_WRITEBACK.
2022-11-09 17:43:06 -06:00
Ross Thompson
ebfee753ca
Updates to fpga constraints.
2022-11-09 13:52:36 -06:00
cturek
d5c5450f8d
Reoredered tests for arch32m
2022-11-09 18:42:00 +00:00
cturek
e7c25f9562
Fixed asign and bsign
2022-11-09 18:41:26 +00:00
Ross Thompson
42c0a10d07
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
9b20bf341e
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
Ross Thompson
fd1ef82310
Fixed bug with fpga makefile.
2022-11-07 09:20:05 -06:00
