Commit Graph

73 Commits

Author SHA1 Message Date
Ross Thompson
e06fb923a1 Better solution to the integer divider interrupt interaction. 2022-01-12 14:22:18 -06:00
Ross Thompson
11f1613d59 Added additional fsm to ILA. 2022-01-12 14:17:16 -06:00
Ross Thompson
d8173745bb Possible fix for the TrapM DTLBMiss suppression. 2022-01-12 14:17:16 -06:00
Ross Thompson
cd75bf98e1 If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
b294f1fbb0 Oups. My hack for DivE interrupt prevention was wrong. 2022-01-12 14:17:16 -06:00
Ross Thompson
459f4bd3b4 Hack "fix" to prevent interrupt from occuring during an integer divide.
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
960af4b70f Set rv32ic to not use icache. 2022-01-12 14:10:09 -06:00
Ross Thompson
f18684efbf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-12 13:29:19 -06:00
Ross Thompson
786a772444 Improve wavefile by adding performance counters. 2022-01-12 10:53:29 -06:00
Kip Macsai-Goren
c251144460 Fixed PMA regions, Added passing PMA tests to regression 2022-01-10 22:08:26 +00:00
David Harris
3a2b459439 Merged coremark changes 2022-01-10 05:09:28 +00:00
David Harris
401a5b1779 Removed unused coremark_bare 2022-01-10 05:05:55 +00:00
David Harris
39d5570d2c Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark. 2022-01-10 05:04:13 +00:00
Ross Thompson
73c488914f Added icache access and icache miss to performance counters. 2022-01-09 22:56:56 -06:00
Ross Thompson
04ea93aa27 Added performance counters to wavefile. 2022-01-09 22:42:14 -06:00
Ross Thompson
ae927e2bc6 Fixed wavefile.
Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
David Harris
0212260eef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-09 14:39:33 +00:00
Ross Thompson
509a0cd3f8 Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
only at the start of a request.  Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm.  On a miss with write back, the inital fetch is handled correctly.  However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.

The solution is to modify how cpu requests are suppressed.  Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
54d852f6ae renamed regression-wally.py to regression-wally 2022-01-07 17:47:38 +00:00
David Harris
bea6d0856d Testbench directory cleanup 2022-01-07 17:02:16 +00:00
David Harris
120fb7863f Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
David Harris
fedb9d3287 moved proposed-sdc 2022-01-07 12:44:21 +00:00
David Harris
40af3abef9 piplined directory cleanup 2022-01-07 12:43:50 +00:00
David Harris
c97572d209 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-07 05:39:16 +00:00
Ross Thompson
c8d47fc7c3 Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
David Harris
2a64b1bc95 Used .* in wrapper 2022-01-07 05:23:42 +00:00
Ross Thompson
0fddceffa6 Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
assign from the input non translated virtual address.  Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address.  This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
1d8451c2cf Capitalized LSU and IFU, changed MulDiv to MDU 2022-01-07 04:30:00 +00:00
David Harris
0e023e29d8 Code cleanup 2022-01-07 04:07:04 +00:00
Ross Thompson
c9c3bddc6d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-06 17:19:20 -06:00
Ross Thompson
008ac20a43 Minor optimization to cache replacement. 2022-01-06 17:19:14 -06:00
David Harris
08231d4e66 Tests cleanup: 2022-01-06 23:07:22 +00:00
David Harris
cb68548b88 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 23:04:33 +00:00
David Harris
fc4db84bbc Makefile make allclean 2022-01-06 23:04:30 +00:00
David Harris
e5f9fbb238 Fixed multiplier nan boxing bug 2022-01-06 23:03:29 +00:00
Katherine Parry
b3ebce0365 some FPU test fixes 2022-01-06 23:03:20 +00:00
Ross Thompson
e1db967417 Clean up of cachefsm. 2022-01-06 16:32:49 -06:00
David Harris
1c96b22b8f More FP unpacking fix 2022-01-06 22:22:22 +00:00
David Harris
2b8e8707a7 Floating point test cleanup 2022-01-06 21:45:16 +00:00
David Harris
2b4c81fe98 Fixed unpacking bug; regression runs again 2022-01-06 18:22:30 +00:00
David Harris
55e757db03 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 18:10:32 +00:00
David Harris
c9aa21d5a3 FPU debug and configurable logic cleanup 2022-01-06 18:10:25 +00:00
Ross Thompson
d30ad136f3 cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv. 2022-01-05 22:56:18 -06:00
Ross Thompson
365b2715ed More name cleanup in cache. 2022-01-05 22:37:53 -06:00
Ross Thompson
77efcad15b Changed names of address in caches.
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
5a2ae561a7 Updates to support fpga. 2022-01-05 18:07:23 -06:00
Ross Thompson
3517db6b64 Fixed xilinx synth error with $error in extend.sv 2022-01-05 17:48:08 -06:00
Ross Thompson
fb3207fc72 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-05 16:57:29 -06:00
Ross Thompson
8d33bf0b4a Slower but correct implementation of flush. 2022-01-05 16:57:22 -06:00
David Harris
e33db012ba Reinstated many arch f/d tests that had failed because of memfile issues 2022-01-05 22:44:10 +00:00