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Merged coremark changes

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This commit is contained in:
David Harris 2022-01-10 05:09:28 +00:00
commit 3a2b459439
14 changed files with 474 additions and 553 deletions
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6
benchmarks/riscv-coremark/Makefile
View File

@ -6,8 +6,8 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
work/coremark.bare.riscv.memfile: work/coremark.bare.riscv work/coremark.bare.riscv.objdump
riscv64-unknown-elf-elf2hex --bit-width 64 --input "work/coremark.bare.riscv" --output "work/coremark.bare.riscv.memfile"
work/coremark.bare.riscv.memfile: work/coremark.bare.riscv
riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@
work/coremark.bare.riscv.objdump: work/coremark.bare.riscv
riscv64-unknown-elf-objdump -D work/coremark.bare.riscv > work/coremark.bare.riscv.objdump
@ -15,7 +15,7 @@ work/coremark.bare.riscv.objdump: work/coremark.bare.riscv
work/coremark.bare.riscv: $(sources) Makefile
# make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fno-toplevel-reorder --param=max-inline-insns-size=128 -fipa-pta"
# These flags were used by WD on CoreMark
make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta "
make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta "
# -fno-toplevel-reorder --param=max-inline-insns-size=128 " # adding this bit caused a compiler error
mkdir -p work/
mv $(cmbase)/coremark.bare.riscv work/

78
pipelined/regression/wally-coremark.do
View File

@ -38,82 +38,8 @@ vsim workopt
mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/ram/ram/RAM
view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave /testbench/clk
add wave /testbench/reset
add wave -divider
#add wave /testbench/dut/hart/ebu/IReadF
#add wave /testbench/dut/hart/DataStall
#add wave /testbench/dut/hart/InstrStall
#add wave /testbench/dut/hart/StallF
#add wave /testbench/dut/hart/StallD
#add wave /testbench/dut/hart/FlushD
#add wave /testbench/dut/hart/FlushE
#add wave /testbench/dut/hart/FlushM
#add wave /testbench/dut/hart/FlushW
add wave -divider Fetch
add wave -hex /testbench/dut/hart/ifu/PCF
#add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
add wave /testbench/InstrFName
add wave -divider Decode
add wave -hex /testbench/dut/hart/ifu/PCD
add wave -hex /testbench/dut/hart/ifu/InstrD
add wave /testbench/InstrDName
add wave -divider Execute
add wave -hex /testbench/dut/hart/ifu/PCE
add wave -hex /testbench/dut/hart/ifu/InstrE
add wave /testbench/InstrEName
add wave -divider Memory
add wave -hex /testbench/dut/hart/ifu/PCM
add wave -hex /testbench/dut/hart/ifu/InstrM
add wave /testbench/InstrMName
add wave -divider Write
add wave -hex /testbench/PCW
add wave -hex /testbench/InstrW
add wave /testbench/InstrWName
#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
#add wave /testbench/dut/hart/ieu/dp/PCSrcE
add wave -divider Regfile_signals
#add wave /testbench/dut/uncore/ram/memwrite
#add wave -hex /testbench/dut/uncore/HADDR
#add wave -hex /testbench/dut/uncore/HWDATA
#add wave -divider
#add wave -hex /testbench/PCW
#add wave /testbench/InstrWName
#add wave /testbench/dut/hart/ieu/dp/RegWriteW
#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
#add wave -hex /testbench/dut/hart/ieu/dp/RdW
add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
add wave -divider Regfile_itself
add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
add wave -divider RAM
#add wave -hex -r /testbench/dut/uncore/ram/RAM
add wave -divider Misc
add wave -divider
#add wave -hex -r /testbench/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {100 ps}
configure wave -namecolwidth 250
configure wave -valuecolwidth 120
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
set DefaultRadix hexadecimal
-- Run the Simulation
#run 7402000
#run 12750
do wave.do
run -all
#run 21400
quit
#quit

510
pipelined/regression/wave.do
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File diff suppressed because one or more lines are too long

25
pipelined/src/ifu/ifu.sv
View File

@ -79,7 +79,9 @@ module ifu (
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
output logic InstrAccessFaultF
output logic InstrAccessFaultF,
output logic ICacheAccess,
output logic ICacheMiss
);
logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
@ -242,20 +244,6 @@ module ifu (
logic [1:0] IFURWF;
assign IFURWF = CacheableF ? 2'b10 : 2'b00;
/* -----\/----- EXCLUDED -----\/-----
icache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS))
icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
.ICacheFetchLine,
.IFURWF(IFURWF), //aways read
.PCNextF(PCNextFMux),
.PCPF(PCPF),
.PCF(PCFMux),
.InvalidateICacheM);
-----/\----- EXCLUDED -----/\----- */
logic [`XLEN-1:0] FinalInstrRawF_FIXME;
cache #(.LINELEN(`ICACHE_LINELENINBITS),
@ -266,8 +254,8 @@ module ifu (
.CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(),
.ReadDataLineSets(),
.CacheMiss(),
.CacheAccess(),
.CacheMiss(ICacheMiss),
.CacheAccess(ICacheAccess),
.FinalWriteData('0),
.RW(IFURWF),
.Atomic(2'b00),
@ -281,9 +269,10 @@ module ifu (
end else begin
assign ICacheFetchLine = 0;
assign ICacheBusAdr = 0;
//assign CompressedF = 0; //?
assign ICacheStallF = 0;
assign FinalInstrRawF = 0;
assign ICacheAccess = CacheableF;
assign ICacheMiss = CacheableF;
end
// select between dcache and direct from the BUS. Always selected if no dcache.

2
pipelined/src/lsu/lsu.sv
View File

@ -318,7 +318,7 @@ module lsu
end else begin : passthrough
assign ReadDataWordM = 0;
assign DCacheStall = 0;
assign DCacheMiss = 1;
assign DCacheMiss = CacheableM;
assign DCacheAccess = CacheableM;
assign DCacheCommittedM = 0;
assign DCacheWriteLine = 0;

4
pipelined/src/privileged/csr.sv
View File

@ -53,6 +53,8 @@ module csr #(parameter
input logic [4:0] InstrClassM,
input logic DCacheMiss,
input logic DCacheAccess,
input logic ICacheMiss,
input logic ICacheAccess,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
output logic [1:0] STATUS_MPP,
@ -131,7 +133,7 @@ module csr #(parameter
.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
.InstrValidM, .LoadStallD, .CSRMWriteM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.InstrClassM, .DCacheMiss, .DCacheAccess,
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);

8
pipelined/src/privileged/csrc.sv
View File

@ -52,6 +52,8 @@ module csrc #(parameter
input logic [4:0] InstrClassM,
input logic DCacheMiss,
input logic DCacheAccess,
input logic ICacheMiss,
input logic ICacheAccess,
input logic [11:0] CSRAdrM,
input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] CSRWriteValM,
@ -98,8 +100,10 @@ module csrc #(parameter
assign CounterEvent[9] = InstrClassM[3] & InstrValidNotFlushedM;
assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM;
assign CounterEvent[11] = DCacheAccess;
assign CounterEvent[12] = DCacheMiss;
assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
assign CounterEvent[12] = DCacheMiss;
assign CounterEvent[13] = ICacheAccess;
assign CounterEvent[14] = ICacheMiss;
assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
end
// Counter update and write logic

4
pipelined/src/privileged/privileged.sv
View File

@ -48,6 +48,8 @@ module privileged (
input logic [4:0] InstrClassM,
input logic DCacheMiss,
input logic DCacheAccess,
input logic ICacheMiss,
input logic ICacheAccess,
input logic PrivilegedM,
input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
@ -162,7 +164,7 @@ module privileged (
.MTIME_CLINT,
.InstrValidM, .FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess,
.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.NextPrivilegeModeM, .PrivilegeModeW,
.CauseM, .NextFaultMtvalM, .STATUS_MPP,
.STATUS_SPP, .STATUS_TSR,

5
pipelined/src/wally/wallypipelinedhart.sv
View File

@ -159,6 +159,8 @@ module wallypipelinedhart (
logic PendingInterruptM;
logic DCacheMiss;
logic DCacheAccess;
logic ICacheMiss;
logic ICacheAccess;
logic BreakpointFaultM, EcallFaultM;
@ -171,6 +173,7 @@ module wallypipelinedhart (
// Fetch
.IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr,
.IFUBusRead, .IFUStallF,
.ICacheAccess, .ICacheMiss,
// Execute
.PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
@ -322,7 +325,7 @@ module wallypipelinedhart (
.FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM,
.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
.LoadMisalignedFaultM, .StoreMisalignedFaultM,

2
pipelined/testbench/testbench-coremark_bare.sv
View File

@ -87,7 +87,7 @@ module testbench();
// Track names of instructions
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
dut.hart.ifu.icache.icache.readdata.FinalInstrRawF, // *** is there a better name
dut.hart.ifu.FinalInstrRawF,
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
dut.hart.ifu.InstrM, InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);

69
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.S
View File

@ -288,46 +288,37 @@ test_loop:
lw x30, 8(x5) # fetch test case flag
addi x5, x5, 12 # set x5 to next test case
# case statements for which test behavior to perform.
# *** We would use the same table method as the test types and trap handler,
# but that presents problems with virtual addressing and updating the address after the la command
slli x30, x30, 2 # multiply test type by 4 to index into jump table
la x7, test_jump_table # load base address of jump table
add x7, x7, x30 # get address of jump table entry
jr x7 # jump to relevant test
# x30 Value : Function : Fault output value : Normal output values
# ----------:---------------------------------------:------------------------:------------------------------------------------------
li x7, 0x0 # : : :
beq x30, x7, write32_test # 0x0 : Write 32 bits to address : 0xf : None
li x7, 0x12 # : : :
beq x30, x7, write16_test # 0x12 : Write 16 bits to address : 0xf : None
li x7, 0x13 # : : :
beq x30, x7, write08_test # 0x13 : Write 8 bits to address : 0xf : None
li x7, 0x1 # : : :
beq x30, x7, read32_test # 0x1 : Read 32 bits from address : 0xd, 0xbad : readvalue in hex
li x7, 0x15 # : : :
beq x30, x7, read16_test # 0x15 : Read 16 bitsfrom address : 0xd, 0xbad : readvalue in hex
li x7, 0x16 # : : :
beq x30, x7, read08_test # 0x16 : Read 8 bitsfrom address : 0xd, 0xbad : readvalue in hex
li x7, 0x2 # : : :
beq x30, x7, executable_test # 0x2 : test executable at address : 0xc, 0xbad : leading 12 bits of the li instr written to address. In general this is 0x111. (be sure to also write a return instruction)
li x7, 0x3 # : : :
beq x30, x7, terminate_test # 0x3 : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
li x7, 0x4 # : : :
beq x30, x7, goto_baremetal # 0x4 : satp.MODE = bare metal : None : None
li x7, 0x5 # : : :
beq x30, x7, goto_sv32 # 0x5 : satp.MODE = sv32 : None : None
li x7, 0x7 # : : :
beq x30, x7, write_mxr_sum # 0x7 : write sstatus.[19:18] = MXR, SUM bits : None : None
li x7, 0xD # : : :
beq x30, x7, write_pmpcfg_0 # 0xD : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value
li x7, 0xE # : : :
beq x30, x7, write_pmpaddr_0 # 0xE : Write one of the pmpaddr csr's : None : readback of pmpaddr value
li x7, 0x8 # : : :
beq x30, x7, goto_m_mode # 0x8 : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
li x7, 0x9 # : : :
beq x30, x7, goto_s_mode # 0x9 : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
li x7, 0xA # : : :
beq x30, x7, goto_u_mode # 0xA : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
# ------------------------------------------------------------------------------------------------------------------------------------
j terminate_test # default case: break
test_jump_table:
# x30 Value : Function : Fault output value : Normal output values
# ----------:---------------------------------------:------------------------:------------------------------------------------------
j write32_test # 0x0 : Write 32 bits to address : 0xf : None
j read32_test # 0x1 : Read 32 bits from address : 0xd, 0xbad : readvalue in hex
j executable_test # 0x2 : test executable at address : 0xc, 0xbad : leading 12 bits of the li instr written to address. In general this is 0x111. (be sure to also write a return instruction)
j terminate_test # 0x3 : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
j goto_baremetal # 0x4 : satp.MODE = bare metal : None : None
j goto_sv32 # 0x5 : satp.MODE = sv32 : None : None
j segfault # 0x6 : Segfault, undefined test
j write_mxr_sum # 0x7 : write sstatus.[19:18] = MXR, SUM bits : None : None
j goto_m_mode # 0x8 : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
j goto_s_mode # 0x9 : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
j goto_u_mode # 0xA : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
j segfault # 0xB : Segfault, undefined test
j segfault # 0xC : Segfault, undefined test
j write_pmpcfg_0 # 0xD : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value
j write_pmpaddr_0 # 0xE : Write one of the pmpaddr csr's : None : readback of pmpaddr value
j segfault # 0xF : Segfault, undefined test
j segfault # 0x10 : Segfault, undefined test
j segfault # 0x11 : Segfault, undefined test
j write16_test # 0x12 : Write 16 bits to address : 0xf : None
j write08_test # 0x13 : Write 8 bits to address : 0xf : None
j segfault # 0x14 : Segfault, undefined test
j read16_test # 0x15 : Read 16 bits from address : 0xd, 0xbad : readvalue in hex
j read08_test # 0x16 : Read 8 bits from address : 0xd, 0xbad : readvalue in hex
write32_test:
# address to write in x28, word value in x29

96
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output
View File

@ -82,11 +82,15 @@ beef00c1
00000000
00000bad
00000000
beef00c4
00000007
00000000
000000c5
00000005
00000000
000000c6
00000bad
00000000
00000001
00000000
00000bad
00000000
00000007
00000000
@ -98,7 +102,47 @@ beef00c4
00000000
00000bad
00000000
00000009
00000007
00000000
00000005
00000000
00000bad
00000000
00000001
00000000
00000bad
00000000
00000007
00000000
00000005
00000000
00000bad
00000000
00000001
00000000
00000bad
00000000
00000007
00000000
00000005
00000000
00000bad
00000000
00000001
00000000
00000bad
00000000
00000007
00000000
00000005
00000000
00000bad
00000000
00000001
00000000
00000bad
00000000
0000000b
00000000
deadbeef
deadbeef
@ -978,47 +1022,3 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

141
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S
View File

@ -21,6 +21,19 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#define BOOTROM_BASE 0x00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
#define BOOTROM_RANGE 0x00000FFF
#define RAM_BASE 0x80000000
#define RAM_RANGE 0x7FFFFFFF
#define CLINT_BASE 0x02000000
#define CLINT_RANGE 0x0000FFFF
#define GPIO_BASE 0x10012000
#define GPIO_RANGE 0x000000FF
#define UART_BASE 0x10000000
#define UART_RANGE 0x00000007
#define PLIC_BASE 0x0C000000
#define PLIC_RANGE 0x03FFFFFF
#include "WALLY-TEST-LIB-64.S"
// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions
// Ideally this should mean that a test can be written by simply adding .8byte statements as below.
@ -48,101 +61,95 @@
# | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO |
# | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO |
# | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO |
# | DRAM | 0x80000000 | Any | YES | YES | YES | YES | YES | YES |
# ************** Cacheable, Idempotent, Atomic tests are not implemented yet.
# *** Cacheable, Idempotent, Atomic tests are not implemented yet.
# ----------------- ROM ---------------------
# *** the rom is read only and these read tests depend on reading a known value out of memory.
# Is there some guaranteed value that I can read out of the ROM
# otherwise the read test can be modified to just check that the read happened,
# not necessarily that it got a known value out of memory. This feels hacky and Id be interested in other options.
# ROM goes untested because it isn't writeable and these tests rely on writing a known value to memory.
# .8byte 0x1000, 0x0000DEADBEEF0000, 0x0 # 64-bit write: store access fault
# .8byte 0x1000, 0x0000DEADBEEF0000, 0x1 # 64-bit read: success
# .8byte 0x1000, 0x0000DEADBEEF0001, 0x11 # 32-bit write: store access fault
# .8byte 0x1000, 0x0000DEADBEEF0001, 0x14 # 32-bit read: success
# .8byte 0x1000, 0x0000DEADBEEF0002, 0x12 # 16-bit write: store access fault
# .8byte 0x1000, 0x0000DEADBEEF0002, 0x15 # 16-bit read: success
# .8byte 0x1000, 0x0000DEADBEEF0003, 0x13 # 08-bit write: store access fault
# .8byte 0x1000, 0x0000DEADBEEF0003, 0x16 # 08-bit read: success
# # *** similar problem with the execute tests. Impossible to write the needed executable code into rom once the program's running
# .8byte 0x1000, 0x111, 0x2 # execute: success
# ----------------- CLINT ---------------------
.8byte 0x2000000, 0x0000DEADBEEF00B4, 0x0 # 64-bit write: success
.8byte 0x2000000, 0x0000DEADBEEF00B4, 0x1 # 64-bit read: success
.8byte 0x2000000, 0x0000DEADBEEF00B5, 0x11 # 32-bit write: success
.8byte 0x2000000, 0x0000DEADBEEF00B5, 0x14 # 32-bit read: success
.8byte 0x2000000, 0x0000DEADBEEF00B6, 0x12 # 16-bit write: success
.8byte 0x2000000, 0x0000DEADBEEF00B6, 0x15 # 16-bit read: success
.8byte 0x2000000, 0x0000DEADBEEF00B7, 0x13 # 08-bit write: success
.8byte 0x2000000, 0x0000DEADBEEF00B7, 0x16 # 08-bit read: success
.8byte CLINT_BASE, 0xEEEEEEEEEEEEEEEE, 0x0 # 64-bit write: success
.8byte CLINT_BASE, 0x0000DEADBEEF00B4, 0x1 # 64-bit read: success
.8byte CLINT_BASE, 0x0000DEADBEEF00B5, 0x11 # 32-bit write: success
.8byte CLINT_BASE, 0x0000DEADBEEF00B5, 0x14 # 32-bit read: success
.8byte CLINT_BASE, 0x0000DEADBEEF00B6, 0x12 # 16-bit write: success
.8byte CLINT_BASE, 0x0000DEADBEEF00B6, 0x15 # 16-bit read: success
.8byte CLINT_BASE, 0x0000DEADBEEF00B7, 0x13 # 08-bit write: success
.8byte CLINT_BASE, 0x0000DEADBEEF00B7, 0x16 # 08-bit read: success
.8byte 0x2000000, 0xbad, 0x2 # execute: instruction access fault
.8byte CLINT_BASE, 0xbad, 0x2 # execute: instruction access fault
# ----------------- PLIC ---------------------
.8byte 0xC000000, 0x0000DEADBEEF00B8, 0x0 # 64-bit write: store access fault
.8byte 0xC000000, 0x0000DEADBEEF00B8, 0x1 # 64-bit read: load access fault
.8byte 0xC000000, 0x0000DEADBEEF00B9, 0x11 # 32-bit write: success
.8byte 0xC000000, 0x0000DEADBEEF00B9, 0x14 # 32-bit read: success
.8byte 0xC000000, 0x0000DEADBEEF00BA, 0x12 # 16-bit write: store access fault
.8byte 0xC000000, 0x0000DEADBEEF00BA, 0x15 # 16-bit read: load access fault
.8byte 0xC000000, 0x0000DEADBEEF00BB, 0x13 # 08-bit write: store access fault
.8byte 0xC000000, 0x0000DEADBEEF00BB, 0x16 # 08-bit read: load access fault
.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x0 # 64-bit write: store access fault
.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x1 # 64-bit read: load access fault
.8byte PLIC_BASE, 0x0000DEADBEEF00B9, 0x11 # 32-bit write: success
.8byte PLIC_BASE, 0x0000DEADBEEF00B9, 0x14 # 32-bit read: success
.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x12 # 16-bit write: store access fault
.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x15 # 16-bit read: load access fault
.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x13 # 08-bit write: store access fault
.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x16 # 08-bit read: load access fault
.8byte 0xC000000, 0xbad, 0x2 # execute: instruction access fault
.8byte PLIC_BASE, 0xbad, 0x2 # execute: instruction access fault
# ----------------- UART0 ---------------------
.8byte 0x10000000, 0x0000DEADBEEF00BC, 0x0 # 64-bit write: store access fault
.8byte 0x10000000, 0x0000DEADBEEF00BC, 0x1 # 64-bit read: load access fault
.8byte 0x10000000, 0x0000DEADBEEF00BD, 0x11 # 32-bit write: store access fault
.8byte 0x10000000, 0x0000DEADBEEF00BD, 0x14 # 32-bit read: load access fault
.8byte 0x10000000, 0x0000DEADBEEF00BE, 0x12 # 16-bit write: store access fault
.8byte 0x10000000, 0x0000DEADBEEF00BE, 0x15 # 16-bit read: load access fault
.8byte 0x10000000, 0x0000DEADBEEF00BF, 0x13 # 08-bit write: success
.8byte 0x10000000, 0x0000DEADBEEF00BF, 0x16 # 08-bit read: success
.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x0 # 64-bit write: store access fault
.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x1 # 64-bit read: load access fault
.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x11 # 32-bit write: store access fault
.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x14 # 32-bit read: load access fault
.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x12 # 16-bit write: store access fault
.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x15 # 16-bit read: load access fault
.8byte UART_BASE, 0x0000DEADBEEF00BF, 0x13 # 08-bit write: success
.8byte UART_BASE, 0x0000DEADBEEF00BF, 0x16 # 08-bit read: success
.8byte 0x10000000, 0xbad, 0x2 # execute: instruction access fault
.8byte UART_BASE, 0xbad, 0x2 # execute: instruction access fault
# ----------------- GPIO ---------------------
.8byte 0x1012000, 0x0000DEADBEEF00C0, 0x0 # 64-bit write: store access fault
.8byte 0x1012000, 0x0000DEADBEEF00C0, 0x1 # 64-bit read: load access fault
.8byte 0x1012000, 0x0000DEADBEEF00C1, 0x11 # 32-bit write: success
.8byte 0x1012000, 0x0000DEADBEEF00C1, 0x14 # 32-bit read: success
.8byte 0x1012000, 0x0000DEADBEEF00C2, 0x12 # 16-bit write: store access fault
.8byte 0x1012000, 0x0000DEADBEEF00C2, 0x15 # 16-bit read: load access fault
.8byte 0x1012000, 0x0000DEADBEEF00C3, 0x13 # 08-bit write: store access fault
.8byte 0x1012000, 0x0000DEADBEEF00C3, 0x16 # 08-bit read: load access fault
.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x0 # 64-bit write: store access fault
.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x1 # 64-bit read: load access fault
.8byte GPIO_BASE, 0x0000DEADBEEF00C1, 0x11 # 32-bit write: success
.8byte GPIO_BASE, 0x0000DEADBEEF00C1, 0x14 # 32-bit read: success
.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x12 # 16-bit write: store access fault
.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x15 # 16-bit read: load access fault
.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x13 # 08-bit write: store access fault
.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x16 # 08-bit read: load access fault
.8byte 0x1012000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- DRAM ---------------------
# the following is already tested by the fact that this test runs without error:
# 64 bit reads and writes into DRAM,
# Execution in DRAM
# offset by 0xf000 to avoid overwriting the program
.8byte 0x8000F000, 0x0000DEADBEEF00C4, 0x11 # 32-bit write: success
.8byte 0x8000F000, 0x0000DEADBEEF00C4, 0x14 # 32-bit read: success
.8byte 0x8000F000, 0x0000DEADBEEF00C5, 0x12 # 16-bit write: success
.8byte 0x8000F000, 0x0000DEADBEEF00C5, 0x15 # 16-bit read: success
.8byte 0x8000F000, 0x0000DEADBEEF00C6, 0x13 # 08-bit write: success
.8byte 0x8000F000, 0x0000DEADBEEF00C6, 0x16 # 08-bit read: success
.8byte GPIO_BASE, 0xbad, 0x2 # execute: instruction access fault
# ----------------- Inaccessible ---------------------
# show that load, store, and jalr cause faults in a region not defined by PMAs.
# *** should I go through every possible inaccessible region of memory or is one just fine?
# Tests 'random' place in unimplemented memory
.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault
.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault
.8byte 0x1000, 0x111, 0x2 # execute: instruction access fault
.8byte 0xD000000, 0x111, 0x2 # execute: instruction access fault
# Tests just past the end of each peripheral
.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault
.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault
.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x111, 0x2 # execute: instruction access fault
.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault
.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault
.8byte (CLINT_BASE+CLINT_RANGE+1), 0x111, 0x2 # execute: instruction access fault
.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00C7, 0x11 # 32-bit write: store access fault
.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00C7, 0x14 # 32-bit read: load access fault
.8byte (PLIC_BASE+PLIC_RANGE+1), 0x111, 0x2 # execute: instruction access fault
.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00C7, 0x13 # 08-bit write: store access fault
.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00C7, 0x16 # 08-bit read: load access fault
.8byte (UART_BASE+UART_RANGE+1), 0x111, 0x2 # execute: instruction access fault
.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00C7, 0x11 # 32-bit write: store access fault
.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00C7, 0x14 # 32-bit read: load access fault
.8byte (GPIO_BASE+GPIO_RANGE+1), 0x111, 0x2 # execute: instruction access fault
.8byte 0x0, 0x0, 0x3 // terminate tests

77
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.S
View File

@ -293,53 +293,38 @@ test_loop:
ld x30, 16(x5) # fetch test case flag
addi x5, x5, 24 # set x5 to next test case
# case statements for which test behavior to perform.
# *** We would use the same table method as the test types and trap handler,
# but using the la command to load the base of the table loads only the physical address
# So it doesn't work with virtual memory.
# x30 Value : Function : Fault output value : Normal output values
# ----------:---------------------------------------:------------------------:------------------------------------------------------
li x7, 0x0 # : : :
beq x30, x7, write64_test # 0x0 : Write 64 bits to address : 0xf : None
li x7, 0x11 # : : :
beq x30, x7, write32_test # 0x11 : Write 32 bits to address : 0xf : None
li x7, 0x12 # : : :
beq x30, x7, write16_test # 0x12 : Write 16 bits to address : 0xf : None
li x7, 0x13 # : : :
beq x30, x7, write08_test # 0x13 : Write 8 bits to address : 0xf : None
li x7, 0x1 # : : :
beq x30, x7, read64_test # 0x1 : Read 64 bits from address : 0xd, 0xbad : readvalue in hex
li x7, 0x14 # : : :
beq x30, x7, read32_test # 0x14 : Read 32 bitsfrom address : 0xd, 0xbad : readvalue in hex
li x7, 0x15 # : : :
beq x30, x7, read16_test # 0x15 : Read 16 bitsfrom address : 0xd, 0xbad : readvalue in hex
li x7, 0x16 # : : :
beq x30, x7, read08_test # 0x16 : Read 8 bitsfrom address : 0xd, 0xbad : readvalue in hex
li x7, 0x2 # : : :
beq x30, x7, executable_test # 0x2 : test executable on virtual page : 0xc, 0xbad : value of x7 modified by exectuion code (usually 0x111)
li x7, 0x3 # : : :
beq x30, x7, terminate_test # 0x3 : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
li x7, 0x4 # : : :
beq x30, x7, goto_baremetal # 0x4 : satp.MODE = bare metal : None : None
li x7, 0x5 # : : :
beq x30, x7, goto_sv39 # 0x5 : satp.MODE = sv39 : None : None
li x7, 0x6 # : : :
beq x30, x7, goto_sv48 # 0x6 : satp.MODE = sv48 : None : None
li x7, 0x7 # : : :
beq x30, x7, write_mxr_sum # 0x7 : write sstatus.[19:18] = MXR, SUM bits : None : None
li x7, 0xD # : : :
beq x30, x7, write_pmpcfg_0 # 0xD : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value
li x7, 0xE # : : :
beq x30, x7, write_pmpaddr_0 # 0xE : Write one of the pmpaddr csr's : None : None
li x7, 0x8 # : : :
beq x30, x7, goto_m_mode # 0x8 : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
li x7, 0x9 # : : :
beq x30, x7, goto_s_mode # 0x9 : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
li x7, 0xA # : : :
beq x30, x7, goto_u_mode # 0xA : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
# ------------------------------------------------------------------------------------------------------------------------------------
j terminate_test # default case: break
slli x30, x30, 2 # multiply test type by 4 to index into jump table
la x7, test_jump_table # load base address of jump table
add x7, x7, x30 # get address of jump table entry
jr x7 # jump to relevant test
test_jump_table:
# x30 Value : Function : Fault output value : Normal output values
# ----------:---------------------------------------:------------------------:------------------------------------------------------
j write64_test # 0x0 : Write 64 bits to address : 0xf : None
j read64_test # 0x1 : Read 64 bits from address : 0xd, 0xbad : readvalue in hex
j executable_test # 0x2 : test executable on virtual page : 0xc, 0xbad : value of x7 modified by exectuion code (usually 0x111)
j terminate_test # 0x3 : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
j goto_baremetal # 0x4 : satp.MODE = bare metal : None : None
j goto_sv39 # 0x5 : satp.MODE = sv39 : None : None
j goto_sv48 # 0x6 : satp.MODE = sv48 : None : None
j write_mxr_sum # 0x7 : write sstatus.[19:18] = MXR, SUM bits : None : None
j goto_m_mode # 0x8 : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
j goto_s_mode # 0x9 : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
j goto_u_mode # 0xA : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
j segfault # 0xB : Segfault, undefined test
j segfault # 0xC : Segfault, undefined test
j write_pmpcfg_0 # 0xD : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value
j write_pmpaddr_0 # 0xE : Write one of the pmpaddr csr's : None : None
j segfault # 0xF : Segfault, undefined test
j segfault # 0x10 : Segfault, undefined test
j write32_test # 0x11 : Write 32 bits to address : 0xf : None
j write16_test # 0x12 : Write 16 bits to address : 0xf : None
j write08_test # 0x13 : Write 8 bits to address : 0xf : None
j read32_test # 0x14 : Read 32 bitsfrom address : 0xd, 0xbad : readvalue in hex
j read16_test # 0x15 : Read 16 bitsfrom address : 0xd, 0xbad : readvalue in hex
j read08_test # 0x16 : Read 8 bitsfrom address : 0xd, 0xbad : readvalue in hex
write64_test:
# address to write in x28, double value in x29
sd x29, 0(x28)