Ross Thompson cd75bf98e1 If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss. ... This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.		2022-01-12 14:17:16 -06:00
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config	Set rv32ic to not use icache.	2022-01-12 14:10:09 -06:00
fpu-testfloat/FMA/tbgen	Removed more generate statements	2022-01-05 16:25:08 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Improve wavefile by adding performance counters.	2022-01-12 10:53:29 -06:00
src	If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.	2022-01-12 14:17:16 -06:00
srt	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
testbench	Fixed PMA regions, Added passing PMA tests to regression	2022-01-10 22:08:26 +00:00