Ross Thompson 509a0cd3f8 Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu ... only at the start of a request. Pending interrupt was used to start one of these suppressions; however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an interrupt becam pending then the the next request (eviction) made by the cache was also suppressed. This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request to the bus fsm, but the pending interrupt ignored the request. The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt it is better to use interrupt which will be disabled if the dcache is currently processing the evict.		2022-01-07 17:55:34 -06:00
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config	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
fpu-testfloat/FMA/tbgen	Removed more generate statements	2022-01-05 16:25:08 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu	2022-01-07 17:55:34 -06:00
src	Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu	2022-01-07 17:55:34 -06:00
srt	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
testbench	Testbench directory cleanup	2022-01-07 17:02:16 +00:00