David Harris
|
cf0975c937
|
hptw: FSM simplification
|
2021-07-17 11:41:43 -04:00 |
|
David Harris
|
4469b5a4b3
|
hptw: default state should be unreachable
|
2021-07-17 11:33:16 -04:00 |
|
David Harris
|
9cee6c2281
|
hptw: factored Misaligned
|
2021-07-17 11:31:16 -04:00 |
|
David Harris
|
fa12727bbb
|
hptw: factored HPTWRead
|
2021-07-17 11:25:59 -04:00 |
|
David Harris
|
708f8cc3a2
|
hptw: factored HPTWRead
|
2021-07-17 11:25:52 -04:00 |
|
David Harris
|
ef63e1ab52
|
hptw: factored pregen
|
2021-07-17 11:11:10 -04:00 |
|
David Harris
|
880aa1c03a
|
HPTW: more cleanup
|
2021-07-17 04:55:01 -04:00 |
|
David Harris
|
a0f6c9aec1
|
HPTW: factored out DTLBWrite/ITLBWrite
|
2021-07-17 04:44:23 -04:00 |
|
David Harris
|
08e494dd7d
|
HPTW: factored out PageTableENtry
|
2021-07-17 04:40:01 -04:00 |
|
David Harris
|
bd270acdb6
|
more cleaning up FSM
|
2021-07-17 04:35:51 -04:00 |
|
David Harris
|
6d8a6eeba0
|
cleaning up FSM
|
2021-07-17 04:26:41 -04:00 |
|
David Harris
|
330e500442
|
Simplify FSM
|
2021-07-17 04:12:31 -04:00 |
|
David Harris
|
03ef3f7f17
|
Pulled TranslationPAdr mux out of HPTW FSM
|
2021-07-17 04:06:26 -04:00 |
|
David Harris
|
5698433463
|
Simplified bad PTE detection
|
2021-07-17 03:30:17 -04:00 |
|
David Harris
|
ac67342dd4
|
Pulled out shared PTEReg
|
2021-07-17 03:21:09 -04:00 |
|
David Harris
|
86ca9abe42
|
Flip-flop clean-up
|
2021-07-17 03:15:47 -04:00 |
|
David Harris
|
9a15a2f7df
|
Flip-flop clean-up
|
2021-07-17 03:12:24 -04:00 |
|
David Harris
|
8241dd4599
|
Flip-flop clean-up
|
2021-07-17 03:10:17 -04:00 |
|
David Harris
|
a8a5fa4b3c
|
Started pagetablewalker cleanup: combined state flops shared for both RV versions
|
2021-07-17 02:53:52 -04:00 |
|
David Harris
|
b65788d165
|
Replaced separate PageTypeF and PageTypeM with common PageType
|
2021-07-17 02:31:23 -04:00 |
|
Ross Thompson
|
46bce70e42
|
Fixed walker fault interaction with dcache.
|
2021-07-16 12:22:13 -05:00 |
|
Ross Thompson
|
e0f719d513
|
Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
|
2021-07-16 11:12:57 -05:00 |
|
Kip Macsai-Goren
|
abd5b1c02d
|
Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
|
2021-07-15 18:30:29 -04:00 |
|
Ross Thompson
|
e5d624c1fa
|
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
|
2021-07-15 11:56:35 -05:00 |
|
Ross Thompson
|
fa26aec588
|
Merge branch 'main' into dcache
|
2021-07-15 11:55:20 -05:00 |
|
Ross Thompson
|
b9902b0560
|
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
|
2021-07-15 11:00:42 -05:00 |
|
Ross Thompson
|
ba1e1ec231
|
Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
|
2021-07-14 22:26:07 -05:00 |
|
Ross Thompson
|
3e57c899a2
|
Partially working changes to support uncached memory access. Not sure what CommitedM is.
|
2021-07-13 17:24:59 -05:00 |
|
David Harris
|
861ef5e1cb
|
Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
|
2021-07-13 09:32:02 -04:00 |
|
David Harris
|
d3ab6b192a
|
added missing tlbmixer.sv
|
2021-07-09 19:18:23 -04:00 |
|
David Harris
|
5c2f774c35
|
Simplified tlbmixer mux to and-or
|
2021-07-08 23:34:24 -04:00 |
|
David Harris
|
74b6d13195
|
Fixed missing stall in InstrRet counter
|
2021-07-08 20:08:04 -04:00 |
|
Ross Thompson
|
94c3fde724
|
Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.
|
2021-07-08 18:03:52 -05:00 |
|
David Harris
|
4f1a85ca7c
|
Eliminate reserved bits from TLB RAM
|
2021-07-08 17:35:00 -04:00 |
|
David Harris
|
38772de21f
|
Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
|
2021-07-08 16:58:11 -04:00 |
|
David Harris
|
1190729896
|
TLB cleanup to match diagrams
|
2021-07-08 16:52:06 -04:00 |
|
David Harris
|
5d5274ec73
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-07 06:32:29 -04:00 |
|
David Harris
|
2bab3f769b
|
Renamed tlb ReadLines to Matches
|
2021-07-07 06:32:26 -04:00 |
|
Abe
|
b757c96b2d
|
Changed SvMode to SVMode on line 76
|
2021-07-06 23:28:58 -04:00 |
|
David Harris
|
af619dcd75
|
Added ASID matching for CAM
|
2021-07-06 18:56:25 -04:00 |
|
Kip Macsai-Goren
|
8350622f65
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-06 18:54:41 -04:00 |
|
David Harris
|
7d857cf4bd
|
more TLB name touchups
|
2021-07-06 18:39:30 -04:00 |
|
Kip Macsai-Goren
|
e08a578908
|
fixed upper bits page fault signal
|
2021-07-06 18:32:47 -04:00 |
|
David Harris
|
2e2aa2a972
|
connected signals in tlb by name instead of .*
|
2021-07-06 17:22:10 -04:00 |
|
David Harris
|
ee3a321002
|
changed tlbphysicalpagemask to structural
|
2021-07-06 17:16:58 -04:00 |
|
David Harris
|
f960561cbb
|
changed tlbphysicalpagemask to structural
|
2021-07-06 17:08:04 -04:00 |
|
David Harris
|
032c38b7e7
|
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
|
2021-07-06 15:29:42 -04:00 |
|
Ross Thompson
|
3345ed7ff4
|
Merged several of the load/store/instruction access faults inside the mmu.
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
|
2021-07-06 13:43:53 -05:00 |
|
David Harris
|
30fdd7abc8
|
Cleaned up tlb output muxing
|
2021-07-06 10:44:05 -04:00 |
|
David Harris
|
d58cad89a8
|
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
|
2021-07-06 10:38:30 -04:00 |
|