Teo Ene
57f1ca5259
Switched coremark to RV64IM
2021-03-17 22:39:56 -05:00
Teo Ene
d2fe42d6d0
adapted coremark bare testbench to new dtim RAM HDL
2021-03-17 16:59:02 -05:00
Teo Ene
4fd0ecff69
Temporarily reverted my last few commits
2021-03-17 15:16:01 -05:00
Teo Ene
3e849f99a6
fix to last commit
2021-03-17 15:02:15 -05:00
Teo Ene
dfe6df2e00
Added Ross's addr lab stuff to coremark stuff
2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
041439c008
fixing coremark branch prediction
2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
da758e9e14
Merge branch '3_3_2021' into main
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Making sure coremark works with spring break changes
2021-03-17 14:11:37 -04:00
Ross Thompson
3618a39087
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-17 11:07:57 -05:00
Ross Thompson
9f8f0242ca
Added possibly working OSU test bench as a precursor to running a bp benchmark.
...
Fixed a few bugs with the function radix.
2021-03-17 11:06:32 -05:00
Noah Boorstin
bfa7aedd35
busybear: add seperate message on bad memory access becasue its confusing
2021-03-16 21:42:26 -04:00
Domenico Ottolia
d354cbd37d
Add privileged testbench
2021-03-16 20:28:38 -04:00
Noah Boorstin
400791163e
copy Ross's branch predictor preload change into busybear
2021-03-15 18:27:27 -04:00
Ross Thompson
4c8952de6a
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Ross Thompson
7ceef2b0c6
Fixed the issue with the batch mode not working after adding the function radix.
2021-03-12 20:16:03 -06:00
Ross Thompson
6ee97830f7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 14:58:04 -06:00
David Harris
56b690ccb9
Drafted rv32a tests
2021-03-12 00:06:23 -05:00
David Harris
865c103599
64-bit AMO debugged
2021-03-11 23:18:33 -05:00
Ross Thompson
318b642359
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 17:12:21 -06:00
Noah Boorstin
a8b242a6ef
busybear: account for CSR moving
2021-03-11 06:45:14 +00:00
Ross Thompson
845115302e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-10 15:37:02 -06:00
Ross Thompson
f92f766573
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Ross Thompson
dcae90e3ad
I finally think I got the function radix debugger working across both 32 and 64 bit applications.
2021-03-10 14:43:44 -06:00
Ross Thompson
50a92247b3
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 11:00:51 -06:00
David Harris
c2f340681d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
17c0f9629a
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
4a8b689f62
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
c780a25f92
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
93c9c57426
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
Noah Boorstin
86142e764a
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
1a11b60664
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Ross Thompson
264480f258
updated the function radix to look at wally signals.
2021-03-04 17:31:12 -06:00
Noah Boorstin
dfae278ffb
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Noah Boorstin
827dfd774b
Merge branch 'main' into busybear
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Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c
Merge branch 'bp' into main
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Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
bbracker
448cba2a5b
JALR testing
2021-03-04 10:37:30 -05:00
Teo Ene
06be82fc67
Added stop to coremark_bare testbench
2021-03-04 07:47:07 -06:00
Teo Ene
396dc61564
Linux CoreMark and baremetal CoreMark split into two separate tests/configs
2021-03-04 07:44:33 -06:00
Teo Ene
6ebb79abe0
Linux CoreMark is operational
2021-03-04 05:58:18 -06:00
Teo Ene
6031269de8
Implemented fix disucssed with Elizabeth
2021-03-03 18:17:53 -06:00
Teo Ene
4562c61af3
Fix to last push
2021-03-03 15:20:38 -06:00
Noah Boorstin
62b441f3f5
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
965d48afe7
busybear: only check pc when it actually changes
2021-03-01 19:08:35 +00:00
Noah Boorstin
4833b36535
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
David Harris
2543c29839
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Noah Boorstin
bcc0010498
Merge branch 'main' into busybear
2021-02-28 20:45:08 +00:00
Noah Boorstin
db86d20d11
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
e5e345d161
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
37e6a45d76
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
David Harris
cf03afa880
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
