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323 Commits

Author SHA1 Message Date
Ross Thompson
dd84f2958e Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Ross Thompson
bc9c944ba0 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
Ross Thompson
d80ebab941 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Ross Thompson
b4a788c341 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
bbracker
13cf7c0934 linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
Ross Thompson
6bab454b17 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
bbracker
53d545cdfe regression can overcome the fact that buildroots UART prints stuff 2021-06-24 02:00:01 -04:00
bbracker
cee468b21a whoops meant to remove notifications from busybear, not buildroot 2021-06-24 01:54:46 -04:00
bbracker
be962cb1ff overhauled linux testbench and spoofed MTTIME interrupt 2021-06-24 01:42:35 -04:00
David Harris
a514554eeb Reduced complexity of pmpadrdec 2021-06-23 03:03:52 -04:00
bbracker
9b27cd6fb7 added slack notifier for long sims 2021-06-22 08:31:41 -04:00
bbracker
2643130c41 read from MSTATUS workaround because QEMU has incorrect MSTATUS 2021-06-20 10:11:39 -04:00
bbracker
dc26f2a6d0 whoops wavedo typo 2021-06-20 05:36:54 -04:00
bbracker
c77aabdc6f make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
086f031b84 remove lingering busybear stuff from buildroot do files 2021-06-20 00:50:53 -04:00
bbracker
d62d9a7aac make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
David Harris
33312caeb1 Restored wally-busybear testbench now that graphical sim is working 2021-06-18 12:36:25 -04:00
bbracker
4f50dd575d buildroot added to regression because it passes regression 2021-06-18 09:49:30 -04:00
David Harris
336936cc39 Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
bbracker
5b96f7fbd7 making linux waveforms more useful 2021-06-17 08:37:37 -04:00
bbracker
28c6d60150 temporarily removing buildroot from regression until it is regenerated 2021-06-07 13:20:50 -04:00
David Harris
dc0b19dfaa Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
d5ec797ba4 Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Ross Thompson
41a1e6112a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-04 15:16:39 -05:00
Ross Thompson
7406e33b61 Continued I-Cache cleanup. 
Removed strange mux on InstrRawD along with
the select logic.
 2021-06-04 15:14:05 -05:00
Ross Thompson
191f7e61fd Moved I-Cache offset selection mux to icache.sv (top level). 
When we switch to set associative this is will be more efficient.
 2021-06-04 13:49:33 -05:00
Katherine Parry
fc65aedbd6 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Ross Thompson
fdef8df76b Reorganized the icache names. 2021-06-04 12:53:42 -05:00
David Harris
0674f5506e moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
bbracker
4e765ee1c5 expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
bbracker
2c77a13c08 fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
bbracker
39ae743543 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
bbracker
846553ac7d improved PLIC test organization 2021-05-21 15:13:02 -04:00
Katherine Parry
06af239e6c FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
1d3db5ead5 small bit of busybear debug progress 2021-05-19 20:18:00 -04:00
James E. Stine
304e70d3ae Update rv64icfd batch script 2021-05-18 16:01:53 -05:00
David Harris
5da159d17e Removed rv64wally 2021-05-18 14:08:46 -04:00
David Harris
4d264c6f61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/regression/vish_stacktrace.vstf
 2021-05-18 14:01:19 -04:00
bbracker
f00eb22700 fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions 2021-05-17 19:25:54 -04:00
bbracker
e4c90f503a regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench 2021-05-17 18:44:47 -04:00
David Harris
9901f54b15 Deleted vish_stacktrace 2021-05-17 18:39:01 -04:00
Elizabeth Hedenberg
b818ce608a commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
James E. Stine
3d3e3434f6 Cleanup of regression 2021-05-17 16:58:15 -05:00
James E. Stine
865b3ee219 Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
Thomas Fleming
6aa04af38d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-14 07:40:08 -04:00
Thomas Fleming
ea4e76938e Remove busy-mmu and fix missing signal 2021-05-14 07:14:20 -04:00
Jarred Allen
041149eaf7 Minor fixes in regression 2021-05-09 13:57:09 -04:00
Jarred Allen
c7f400262c Fix bug in regression script 2021-05-06 12:56:57 -04:00
Jarred Allen
be029ba02c Clean up regression script and document it 2021-05-04 18:58:59 -04:00
Thomas Fleming
ad40464557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Elizabeth Hedenberg
2d1d929485 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
463ba1a2be coremark directory changes 2021-05-03 19:35:06 -04:00
Ross Thompson
82b4d42f32 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:56:00 -05:00
Ross Thompson
7f38056879 fixed subtle typo in icache fsm. Was messing up hit spill hit. 
I believe the mibench qsort benchmark runs after this icache fix.
 2021-05-03 16:55:36 -05:00
Thomas Fleming
ba1afec621 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:38:13 -04:00
Jarred Allen
7d509252a7 Add lint to regression 2021-05-03 17:32:05 -04:00
Ross Thompson
e145670b15 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 14:53:54 -05:00
Ross Thompson
19a93345b5 Reduced icache to 1 port memory. 2021-05-03 14:47:49 -05:00
Thomas Fleming
cfe64e7c24 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-05-03 14:02:19 -04:00
Ross Thompson
a54c231489 Eliminated extra register and fixed ports to icache. 
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
 2021-05-03 12:04:54 -05:00
bbracker
9ab714e636 small rv64 plic test bugfix 2021-05-03 10:06:44 -04:00
Ross Thompson
c7b97d0339 Added back in function name to wave.do 2021-05-03 09:04:48 -05:00
Noah Boorstin
48d32c1daf rollback regression to 400k instrs for busybear 2021-04-29 20:59:30 -04:00
Thomas Fleming
6e5fc107d9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-29 16:30:00 -04:00
Domenico Ottolia
4fae8088e3 Add medeleg tests 2021-04-29 15:02:36 -04:00
Jarred Allen
ebd9c0ee29 Remove signal which no longer exists from default waves, so sim-wally works 2021-04-29 14:41:10 -04:00
Thomas Fleming
c62fdfb7b3 Remove unused waves from .do files 2021-04-29 02:19:46 -04:00
Thomas Fleming
18e0b353a9 Add mmu waves (commented) to busybear 2021-04-28 20:01:05 -04:00
Ross Thompson
8ae28e7887 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-26 14:28:09 -05:00
Ross Thompson
72363f5c66 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Noah Boorstin
0324329ed9 linux: start using internal branch predictor signal 2021-04-26 14:34:38 -04:00
Noah Boorstin
ee628e388a minor busybear fixes 2021-04-26 13:24:39 -04:00
Ross Thompson
8e5409af66 Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
ba94fa3436 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
1cc0dcc83f progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
6e803b724e Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
86946266cf thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
a3487a9e47 do script refactor 2021-04-24 09:32:09 -04:00
Ross Thompson
27ef10df07 almost working icache. 2021-04-23 16:47:23 -05:00
Jarred Allen
c91f1e197b Remind people to run make allclean when a regression fails 2021-04-22 19:21:00 -04:00
Ross Thompson
020fb65adf Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Ross Thompson
c42399bdb5 Yes. The hack to not repeat the d memory operation fixed this issue. 2021-04-22 15:22:56 -05:00
Jarred Allen
5df6be3ad5 Add buildroot to regression test 2021-04-22 13:34:56 -04:00
Ross Thompson
d8ab7a5de2 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Ross Thompson
7b3735fc25 Fixed for the instruction spills. 2021-04-21 16:47:05 -05:00
Ross Thompson
532c8771ba major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
 2021-04-21 08:39:54 -05:00
Ross Thompson
f3093ac612 Why was the linter messed up? 
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
 2021-04-20 22:06:12 -05:00
Ross Thompson
99424fb983 Progress on icache. Fixed some issues aligning the PC with instruction. Still broken. 2021-04-20 21:19:53 -05:00
Ross Thompson
251ece20fe Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Jarred Allen
850f728cc7 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Noah Boorstin
6954e6df4c buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Noah Boorstin
4f97e9e761 start to add buildroot testbench 
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
 2021-04-16 23:27:29 -04:00
bbracker
368c94d4ff working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Jarred Allen
d99b8f772e Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Ross Thompson
e73e16e57a Created special test for driving the instruction spill error. 
The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code.

0000000000000080 <test_spill>:
  80:	42a9                	li	t0,10
  82:	0001                	nop
  84:	0001                	nop
  86:	0001                	nop
  88:	02bd                	addi	t0,t0,15
  8a:	00628e33          	add	t3,t0,t1
  8e:	01ce8963          	beq	t4,t3,a0 <match>

0000000000000092 <failure>:
  92:	557d                	li	a0,-1
  94:	8082                	ret
  96:	00000013          	nop
  9a:	00000013          	nop
  9e:	0001                	nop

00000000000000a0 <match>:
  a0:	1ffd                	addi	t6,t6,-1
  a2:	fc0f9fe3          	bnez	t6,80 <test_spill>
  a6:	4501                	li	a0,0
  a8:	8082                	ret

Instructions 0x88, 0x8a and 0x8e are read incorrectly.  However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92.  This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates.

The button of wavefile wave.do shows the exact problem in the 'icache'.
 2021-04-08 15:05:08 -05:00
bbracker
005f838b8d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:28:25 -04:00
bbracker
755e2e5771 merge testbench 2021-04-08 14:28:01 -04:00
David Harris
ac8a111d61 merge conflict resolution 2021-04-08 13:53:56 -04:00
David Harris
6a6ccca3c8 fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00