Ross Thompson
cc5a9a015b
Removed mux in PCNextF logic. Minor IFU improvements.
2022-01-26 22:33:26 -06:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
Ross Thompson
fc86651937
IFU simplifications.
2022-01-26 13:54:59 -06:00
David Harris
748375c82f
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
David Harris
21bdce63ff
Testgen working for Lab 2
2022-01-26 18:01:51 +00:00
Ross Thompson
840e814e95
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
David Harris
8d04e83c9f
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
9da1ed4ed9
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
a86a9f5c2a
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
e3136c9a1e
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
7ad2eb009a
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
6a555032eb
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
David Harris
cf50beb958
Start of IFU cleanup
2022-01-25 17:31:53 +00:00
Ross Thompson
8ef70389d3
Added spill support back into the IROM IFU.
2022-01-21 15:50:54 -06:00
Ross Thompson
9982549057
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
0ceaf792ed
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-21 00:12:18 +00:00
David Harris
39d318fb2a
Fixed path to riscvOVPsimPlus
2022-01-21 00:12:14 +00:00
Ross Thompson
e2343699d1
Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
2022-01-20 16:39:54 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
cea09aab98
Removed imperas tests from makefile for now
2022-01-20 14:51:56 +00:00
David Harris
fc932ef0ff
Added top-level make clean
2022-01-20 14:17:26 +00:00
David Harris
d5f12195c8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-20 00:04:27 +00:00
Ross Thompson
acec56c27e
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
David Harris
9b29710990
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-19 00:26:34 +00:00
Ross Thompson
4a75e69457
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
Ross Thompson
28859f959b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-18 17:19:59 -06:00
Ross Thompson
a5f773220e
Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
2022-01-18 17:19:33 -06:00
David Harris
ebf9f5d526
riscvsingle reparittioned to match Ch4
2022-01-17 16:57:32 +00:00
David Harris
55b4423329
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
b63e53bbdb
Defined rv32e and rv32emc configs
2022-01-17 14:01:01 +00:00
David Harris
bd320c2f76
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
325724f556
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
6febce0001
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
fd13272d4c
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
David Harris
db2271b7e0
LSU cleanup
2022-01-15 00:11:30 +00:00
David Harris
dab3c754d7
LSU cleanup
2022-01-15 00:03:03 +00:00
David Harris
2bf4676ff8
LSU cleanup
2022-01-14 23:55:27 +00:00
Ross Thompson
03010845f5
Fixed spillthreshold warning.
2022-01-14 17:23:39 -06:00
Ross Thompson
ba10e9dfe8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-14 17:16:53 -06:00
David Harris
43abf25417
moved fp to tests
2022-01-14 23:05:59 +00:00
David Harris
218a8e6eaa
LSU partitioning
2022-01-14 23:02:28 +00:00
David Harris
ae6792e354
Moved fp tests from testbench to tests/fp
2022-01-14 23:00:46 +00:00
Ross Thompson
73ad5715f4
Cleanup IFU comments.
2022-01-14 15:06:30 -06:00
Ross Thompson
b8f4eb2997
Optimization in the ifu. Please note this optimization is not strictly correct,
...
but is possible. See comments in the ifu source code for details.
2022-01-14 12:16:48 -06:00
Ross Thompson
2e8f5e06bd
More ifu cleanup.
2022-01-14 11:19:12 -06:00
Ross Thompson
3bec276862
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
James E. Stine
e0e30c1e9e
Update to TestFloat for scripts so can run automatically once
...
TestFloat/Softfloat is compiled. Slight change to the README as well.
2022-01-14 09:25:37 -06:00
Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
David Harris
602867f54e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-13 21:46:00 +00:00
