cvw/pipelined
Ross Thompson 42ef1e22e5 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
..
config Updated configs to fix GPIO address to match FU540 2022-01-26 18:16:34 +00:00
fpu-testfloat/FMA/tbgen Removed more generate statements 2022-01-05 16:25:08 +00:00
misc Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
regression 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 2022-01-26 18:23:39 -06:00
src 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 2022-01-26 18:23:39 -06:00
srt Mixed C and assembly language test cases; SRT initial version passing tests 2022-01-13 21:45:54 +00:00
testbench Testgen working for Lab 2 2022-01-26 18:01:51 +00:00