bbracker
83a0a37f8e
make xCOUNTEREN what buildroot expects it to be
2021-06-20 09:22:31 -04:00
David Harris
336936cc39
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
bbracker
2bee4eabab
added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version
2021-06-17 12:09:10 -04:00
bbracker
b65adbea63
enable TIME CSR for 32 bit mode as well
2021-06-17 11:34:16 -04:00
bbracker
5a661a7392
provide time and timeh CSRs based on CLINT's counter
2021-06-17 08:38:30 -04:00
bbracker
9bc5ddf5f2
PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable
2021-06-17 05:19:36 -04:00
bbracker
7b98e7aa2f
mcause test fixes and s-mode interrupt bugfix
2021-06-16 17:37:08 -04:00
David Harris
49b5fa3994
Reverted MIDELEG and MEDELEG to XLEN so busybear passes
2021-06-10 23:47:32 -04:00
David Harris
e41a87be23
Restored counter events
2021-06-10 11:18:58 -04:00
David Harris
3e8026dc21
Configurable number of performance counters
2021-06-10 09:41:26 -04:00
David Harris
01d6ca1e2a
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
David Harris
90e5781471
Start to parameterize number of PMP Entries
2021-06-08 15:29:22 -04:00
bbracker
cc91c774a6
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
2021-06-08 12:41:25 -04:00
bbracker
e7e4105931
* GPIO comprehensive testing
...
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
2021-06-08 12:32:46 -04:00
David Harris
ff62000e2c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
Kip Macsai-Goren
49200bd922
Cleaned up some unused signals
2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
22e8e06ac7
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
Kip Macsai-Goren
1ae529c450
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
David Harris
a26bf37be8
Started MMU
2021-06-04 11:59:14 -04:00
bbracker
2c77a13c08
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
bbracker
39ae743543
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
Katherine Parry
9464c9022d
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
Thomas Fleming
e27bc1cbf7
Clean up MMU code
2021-05-14 07:12:32 -04:00
Thomas Fleming
19ac77d3fa
Fix compiler warning in PMP checker
2021-05-04 15:18:08 -04:00
Thomas Fleming
3a3c88f5b1
Fix bug in PMP checker
...
Now we only enforce PMP regions if at least one is non-null
2021-05-04 03:14:07 -04:00
Thomas Fleming
c9e5af30fa
Disable PMP checker to fix test loops
...
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
2021-05-04 01:56:05 -04:00
Thomas Fleming
ad40464557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Domenico Ottolia
c0f054556c
Fix bug with IllegalInstrFaultM not getting correct value
2021-05-03 22:48:03 -04:00
Thomas Fleming
0254ca7bf6
Adjust attributes in PMA checker
2021-05-03 21:58:32 -04:00
Domenico Ottolia
5ab86a690b
Fix bug that caused stvec to get the wrong value
2021-05-03 17:54:57 -04:00
Thomas Fleming
eda5a267ee
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
cfe64e7c24
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Katherine Parry
db95151d8d
fpu imperas tests run
2021-05-01 02:18:01 +00:00
Domenico Ottolia
d03ca20dc9
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
2021-04-29 20:42:14 -04:00
Thomas Fleming
6e5fc107d9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
ushakya22
9dfbfd5772
fix to pcm bug
2021-04-29 15:21:08 -04:00
Thomas Fleming
5f2bccd88f
Clean up PMA checker and begin PMP checker
2021-04-29 02:20:39 -04:00
Ross Thompson
8e5409af66
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
bbracker
ba94fa3436
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
1cc0dcc83f
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
6e803b724e
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Thomas Fleming
288a6d82ce
Fix HSIZE and HBURST signal widths in PMA checker
2021-04-23 20:11:43 -04:00
Thomas Fleming
da76b80991
Write PCM to TVAL registers
2021-04-22 16:17:57 -04:00
Thomas Fleming
8fee3b3872
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 15:37:19 -04:00
Domenico Ottolia
6b4d2e9634
Fix misa synthesis bug (for real now)
2021-04-22 15:35:20 -04:00
Thomas Fleming
38236e9172
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Domenico Ottolia
fb8f244dab
Fix misa bug
2021-04-22 00:59:07 -04:00
Thomas Fleming
4bae666fa1
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Domenico Ottolia
bf86a809eb
Add tests for sepc register
2021-04-20 23:50:53 -04:00