Ross Thompson
|
afc1bc9c38
|
Moved StoreStall into the hazard unit instead of in the d cache.
|
2021-07-13 13:20:50 -05:00 |
|
Ross Thompson
|
e594eb540d
|
Got the shadow ram cache flush working.
|
2021-07-13 10:03:47 -05:00 |
|
Ross Thompson
|
49f6eec579
|
Team work on solving the dcache data inconsistency problem.
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2021-07-12 23:46:32 -05:00 |
|
Ross Thompson
|
1cc258ade1
|
Progress towards the test bench flush.
|
2021-07-12 14:22:13 -05:00 |
|
Ross Thompson
|
60ed023734
|
Actually writes the correct data now on stores.
|
2021-07-10 17:48:47 -05:00 |
|
Ross Thompson
|
6e7e318396
|
Fixed bug in the LSU pagetable walker interlock.
|
2021-07-06 10:41:36 -05:00 |
|
Ross Thompson
|
2a62ee2e70
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-05 16:07:27 -05:00 |
|
David Harris
|
5f91b339aa
|
Added F_SUPPORTED flag to disable floating point unit when not in MISA
|
2021-07-05 10:30:46 -04:00 |
|
Ross Thompson
|
a252416535
|
Removed the TranslationVAdrQ as it is not necessary.
|
2021-07-04 16:49:34 -05:00 |
|
Ross Thompson
|
7f62808544
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-04 16:19:39 -05:00 |
|
Ross Thompson
|
5b70eb86b0
|
relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.
|
2021-07-04 13:49:38 -05:00 |
|
David Harris
|
9645b023c9
|
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
|
2021-07-04 01:19:38 -04:00 |
|
Ben Bracker
|
59b177beac
|
stop busybear from hanging
|
2021-07-02 17:22:09 -05:00 |
|
Ross Thompson
|
dbd33465e1
|
Merge branch 'main' into bigbadbranch
|
2021-07-02 11:52:26 -05:00 |
|
Ross Thompson
|
61027f650c
|
OMG. It's working!
|
2021-07-01 17:37:53 -05:00 |
|
Ross Thompson
|
2dc349ea6f
|
Fixed the wrong virtual address write into the dtlb.
|
2021-07-01 16:55:16 -05:00 |
|
Ross Thompson
|
88a18496cf
|
Got some stores working in virtual memory.
|
2021-07-01 12:49:09 -05:00 |
|
Ross Thompson
|
002c32d2ad
|
The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
|
2021-06-30 17:02:36 -05:00 |
|
Ross Thompson
|
9ec624702d
|
Major rewrite of ptw to remove combo loop.
|
2021-06-30 16:25:03 -05:00 |
|
Ross Thompson
|
b2d8ba6742
|
The icache now correctly interlocks with the PTW on TLB miss.
|
2021-06-30 11:24:26 -05:00 |
|
Ross Thompson
|
dd84f2958e
|
Page table walker now walks the table.
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
|
2021-06-29 22:33:57 -05:00 |
|
Ross Thompson
|
bc9c944ba0
|
Don't use this branch walker still broken.
|
2021-06-28 17:26:11 -05:00 |
|
Ross Thompson
|
d80ebab941
|
AMO and LR/SC instructions now working correctly.
Page table walking is not working.
|
2021-06-25 15:42:07 -05:00 |
|
Ross Thompson
|
b4a788c341
|
Working through a combo loop.
|
2021-06-25 14:49:27 -05:00 |
|
Ross Thompson
|
d6c19e73f4
|
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
|
2021-06-25 11:05:17 -05:00 |
|
bbracker
|
13cf7c0934
|
linux testbench now ignores HWRITE glitches caused by flush glitches
|
2021-06-25 09:28:52 -04:00 |
|
Ross Thompson
|
6bab454b17
|
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
|
2021-06-24 14:42:59 -05:00 |
|
bbracker
|
53d545cdfe
|
regression can overcome the fact that buildroots UART prints stuff
|
2021-06-24 02:00:01 -04:00 |
|
bbracker
|
cee468b21a
|
whoops meant to remove notifications from busybear, not buildroot
|
2021-06-24 01:54:46 -04:00 |
|
bbracker
|
be962cb1ff
|
overhauled linux testbench and spoofed MTTIME interrupt
|
2021-06-24 01:42:35 -04:00 |
|
David Harris
|
a514554eeb
|
Reduced complexity of pmpadrdec
|
2021-06-23 03:03:52 -04:00 |
|
bbracker
|
9b27cd6fb7
|
added slack notifier for long sims
|
2021-06-22 08:31:41 -04:00 |
|
bbracker
|
2643130c41
|
read from MSTATUS workaround because QEMU has incorrect MSTATUS
|
2021-06-20 10:11:39 -04:00 |
|
bbracker
|
dc26f2a6d0
|
whoops wavedo typo
|
2021-06-20 05:36:54 -04:00 |
|
bbracker
|
c77aabdc6f
|
make buildroot ignore SSTATUS because QEMU did not originally log it
|
2021-06-20 05:31:24 -04:00 |
|
bbracker
|
086f031b84
|
remove lingering busybear stuff from buildroot do files
|
2021-06-20 00:50:53 -04:00 |
|
bbracker
|
d62d9a7aac
|
make buildroot waves only turn on after a user-specified point
|
2021-06-20 00:39:30 -04:00 |
|
David Harris
|
33312caeb1
|
Restored wally-busybear testbench now that graphical sim is working
|
2021-06-18 12:36:25 -04:00 |
|
bbracker
|
4f50dd575d
|
buildroot added to regression because it passes regression
|
2021-06-18 09:49:30 -04:00 |
|
David Harris
|
336936cc39
|
Cleaned up name of MTIME register in CSRC
|
2021-06-18 07:53:49 -04:00 |
|
bbracker
|
5b96f7fbd7
|
making linux waveforms more useful
|
2021-06-17 08:37:37 -04:00 |
|
bbracker
|
28c6d60150
|
temporarily removing buildroot from regression until it is regenerated
|
2021-06-07 13:20:50 -04:00 |
|
David Harris
|
dc0b19dfaa
|
Merge difficulties
|
2021-06-07 09:50:23 -04:00 |
|
David Harris
|
d5ec797ba4
|
Refactored configuration files and renamed testbench-busybear to testbench-linux
|
2021-06-07 09:46:52 -04:00 |
|
Ross Thompson
|
41a1e6112a
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-06-04 15:16:39 -05:00 |
|
Ross Thompson
|
7406e33b61
|
Continued I-Cache cleanup.
Removed strange mux on InstrRawD along with
the select logic.
|
2021-06-04 15:14:05 -05:00 |
|
Ross Thompson
|
191f7e61fd
|
Moved I-Cache offset selection mux to icache.sv (top level).
When we switch to set associative this is will be more efficient.
|
2021-06-04 13:49:33 -05:00 |
|
Katherine Parry
|
fc65aedbd6
|
Double-precision FMA instructions
|
2021-06-04 14:00:11 -04:00 |
|
Ross Thompson
|
fdef8df76b
|
Reorganized the icache names.
|
2021-06-04 12:53:42 -05:00 |
|
David Harris
|
0674f5506e
|
moved shared constants to a shared directory
|
2021-06-03 22:41:30 -04:00 |
|