Ross Thompson
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dcc00ef4b3
|
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
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2022-09-23 11:46:53 -05:00 |
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Ross Thompson
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8a6ca027c2
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The valid and dirty bits match the SRAM implementation now.
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2022-09-22 16:09:09 -05:00 |
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Ross Thompson
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29087812e1
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Solved the sram write first / read first issue. Works correctly with read first now.
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2022-09-22 14:16:26 -05:00 |
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Ross Thompson
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cdc80c1f28
|
Moved other SRAMs to generic/mem.
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2022-09-21 12:36:03 -05:00 |
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Ross Thompson
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91fcca9d17
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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d6fa8d51d7
|
Modified sram1p1rw to support 3 different implementation styles.
SRAM, Read first, and Write first.
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2022-09-21 11:26:00 -05:00 |
|
Ross Thompson
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2ae62c2869
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pipelining of fetch into evict AHB requests.
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2022-09-13 17:51:55 -05:00 |
|
Ross Thompson
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8618045bf2
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Optimization. Able to remove hptw address muxes from the E stage.
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2022-09-08 15:51:18 -05:00 |
|
Ross Thompson
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d6d1c5d66d
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Moved files around.
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2022-08-31 14:08:06 -05:00 |
|
Ross Thompson
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68e54977fe
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More cleanup.
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2022-08-31 11:12:38 -05:00 |
|
Ross Thompson
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0b41ed63f1
|
More simplifications.
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2022-08-31 10:45:16 -05:00 |
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Ross Thompson
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ddd9c507fe
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Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier.
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2022-08-31 10:36:30 -05:00 |
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Ross Thompson
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6122c03e39
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Removed unused old versions of the bus controllers.
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2022-08-31 09:51:54 -05:00 |
|
Ross Thompson
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1c248e5164
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Removed old signals.
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2022-08-31 09:50:39 -05:00 |
|
Ross Thompson
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5b8f888e21
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Maybe fixed it?
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2022-08-30 18:08:34 -05:00 |
|
Ross Thompson
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96793d15c0
|
more progress.
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2022-08-30 17:32:32 -05:00 |
|
Ross Thompson
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63a824cca1
|
More progress.
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2022-08-30 15:27:19 -05:00 |
|
Ross Thompson
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a532eb61ba
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Progress.
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2022-08-30 14:17:00 -05:00 |
|
Ross Thompson
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c8a5d61cbb
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new cache bus fsm not working but lints.
Forgot a few files in the last commit.
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2022-08-30 10:58:07 -05:00 |
|
David Harris
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af2e71046e
|
Fixed rv32e LSU and IFU issues
|
2022-08-25 20:02:38 -07:00 |
|
David Harris
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d7be94fab2
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Cleaned up SelBusWord
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2022-08-25 11:18:13 -07:00 |
|
David Harris
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cd02c894df
|
renamed BusBuffer to FetchBuffer
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2022-08-25 10:44:39 -07:00 |
|
Ross Thompson
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bc0edc7bdf
|
Updated ila signals.
Improve fpga wave config.
added back in the fpga preload.
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2022-08-25 09:03:29 -05:00 |
|
Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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92c3cdc27d
|
Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
|
2022-08-21 15:28:29 -05:00 |
|
Ross Thompson
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96d6218078
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Possible reduction of ignorerequest.
|
2022-08-19 18:07:44 -05:00 |
|
Ross Thompson
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5301444a61
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Changed signal names.
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2022-08-17 16:12:04 -05:00 |
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Ross Thompson
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970a90dd72
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Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
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2022-08-17 16:09:20 -05:00 |
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Ross Thompson
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acd920ae2f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-01 22:09:11 -05:00 |
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Ross Thompson
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f7e64fcd69
|
Fixed fstore2 in cache?
|
2022-08-01 22:04:44 -05:00 |
|
Ross Thompson
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171cf7413b
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Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
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2022-08-01 21:08:14 -05:00 |
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Katherine Parry
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de03954946
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re-added FStore2 in Cache
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2022-07-29 22:54:49 +00:00 |
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Ross Thompson
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f1bd2524b7
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Don't use this commit yet. Untested.
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2022-07-24 15:40:52 -05:00 |
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Ross Thompson
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334008630f
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Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
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2022-07-24 01:20:29 -05:00 |
|
Ross Thompson
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856ac24686
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Removed replay from the config files.
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2022-07-24 00:34:11 -05:00 |
|
Ross Thompson
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458bfbf6f6
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Merged evict dirty clear with flush write back.
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2022-07-24 00:22:43 -05:00 |
|
Ross Thompson
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5cd6c8069d
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signal name cleanup.
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2022-07-22 23:36:27 -05:00 |
|
Ross Thompson
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7d026e02f2
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cache cleanup after removing replay on cpubusy.
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2022-07-22 23:30:25 -05:00 |
|
Ross Thompson
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706bc819e1
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cache fsm cleanup after removal of replay.
|
2022-07-22 23:25:09 -05:00 |
|
Ross Thompson
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0f586c9ed3
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Possible improvement to cache which removes the cpu_busy states.
|
2022-07-22 23:20:37 -05:00 |
|
Ross Thompson
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9868e685a4
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Minor cleanup of cache.
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2022-07-19 23:04:23 -05:00 |
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Ross Thompson
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6c8ac7851e
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Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
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2022-07-19 22:42:25 -05:00 |
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Ross Thompson
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ffda64587c
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Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
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2022-07-18 23:37:18 -05:00 |
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Ross Thompson
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a88543275f
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Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
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2022-07-17 21:05:31 -05:00 |
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Ross Thompson
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3670c47141
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Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
|
2022-07-17 16:20:04 -05:00 |
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Katherine Parry
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2ada8a8bc1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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David Harris
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2bc8ff555b
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added comment about checking SRAM size
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2022-07-10 12:48:51 +00:00 |
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David Harris
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9cb675b2e4
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added comment about RAMs in cacheway
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2022-07-10 12:47:34 +00:00 |
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Katherine Parry
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ca4fe08fd9
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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cd53ae67d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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James Stine
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c5dfefe669
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Update SRAM to /proj/wally
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2022-07-08 08:09:55 -05:00 |
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David Harris
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3f9e662201
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Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
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2022-07-08 08:44:37 +00:00 |
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David Harris
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96a75d7749
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 22:00:59 +00:00 |
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Katherine Parry
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08769e35ae
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modified wally shared
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2022-07-07 21:59:43 +00:00 |
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David Harris
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2f342c430e
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fixing port errors
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2022-07-07 21:57:10 +00:00 |
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Katherine Parry
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0b40f38f02
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added load and store test
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2022-07-07 21:48:51 +00:00 |
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David Harris
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88e3233935
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Preliminary SRAM integration
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2022-07-07 19:56:20 +00:00 |
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Ross Thompson
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bd46cf76a9
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Fixed an issue with direct map cache's nextway logic.
Also found a small error in the replacement policy.
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2022-07-06 18:34:30 -05:00 |
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Madeleine Masser-Frye
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50e9b6ac53
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fixed concatenation syntax
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2022-07-05 22:36:54 +00:00 |
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Katherine Parry
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6baded9121
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added rv32 double precision stores - untested
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2022-06-28 21:33:31 +00:00 |
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David Harris
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f17501ed8c
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Removing unused signals
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2022-05-12 14:36:15 +00:00 |
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David Harris
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3efbd2565a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-03 08:53:35 -07:00 |
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David Harris
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20bbe43a23
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clean up sram1p1rw; still doesn't work on Modelsim 2022.1
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2022-05-03 08:31:54 -07:00 |
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David Harris
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057524b840
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Formatting cache.sv
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2022-05-03 10:53:20 +00:00 |
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David Harris
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9e50c3440d
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sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera
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2022-05-03 03:50:41 -07:00 |
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David Harris
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0df73d203b
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Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.
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2022-05-03 03:45:41 -07:00 |
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Ross Thompson
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396f697d2f
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Hacky fix to prevent ITLBMissF and TrapM bug.
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2022-04-12 17:56:23 -05:00 |
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Ross Thompson
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0a5b500aca
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Changed sram1p1rw to have the same type of bytewrite enables as bram.
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2022-03-30 11:38:25 -05:00 |
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Ross Thompson
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9dce2a0679
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Towards allowing dtim + bus.
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2022-03-11 14:58:21 -06:00 |
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Ross Thompson
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6e24a807f6
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mild cleanup.
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2022-03-11 13:05:47 -06:00 |
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Ross Thompson
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b7a680ec2a
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Moved subcachelineread inside the cache. There is some ugliness to still resolve.
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2022-03-11 12:44:04 -06:00 |
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Ross Thompson
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a18f06c20b
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Moved subcacheline read inside the cache.
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2022-03-11 11:03:36 -06:00 |
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Ross Thompson
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52cc852600
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removed unused parameter.
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2022-03-11 10:43:54 -06:00 |
|
Ross Thompson
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6d914def08
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Name cleanup.
|
2022-03-10 18:44:50 -06:00 |
|
Ross Thompson
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63b1ea88c9
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Signal name cleanup.
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2022-03-10 18:26:58 -06:00 |
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Ross Thompson
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67ef46ea92
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Partially working byte write enables. Works for cache, but not dtim or bus only.
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2022-03-10 16:11:39 -06:00 |
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Ross Thompson
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7a129c75cd
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Added byte write enables to cache SRAMs.
|
2022-03-10 15:48:31 -06:00 |
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Ross Thompson
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7b96b3f73c
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Moved cacheable signal into cache.
|
2022-03-08 16:34:02 -06:00 |
|
David Harris
|
2cea3349ad
|
LSU/Cache code review notes
|
2022-03-04 00:07:31 +00:00 |
|
Ross Thompson
|
6076f90bbc
|
Cache mods to be consistant with diagrams.
|
2022-02-14 12:40:51 -06:00 |
|
Ross Thompson
|
e852cb8a31
|
Eliminated more ports in cacheway.
|
2022-02-13 15:53:46 -06:00 |
|
Ross Thompson
|
1d7949513d
|
More cache cleanup.
|
2022-02-13 15:47:27 -06:00 |
|
Ross Thompson
|
7ffbc6b2ab
|
Changed names of signals in cache.
|
2022-02-13 15:06:18 -06:00 |
|
Ross Thompson
|
a5ad4331ec
|
More cache cleanup.
|
2022-02-13 12:38:39 -06:00 |
|
Ross Thompson
|
dd944265aa
|
Formating improvements to cache.
|
2022-02-11 23:10:58 -06:00 |
|
Ross Thompson
|
bf173b035c
|
More cache simplifications.
|
2022-02-11 22:54:05 -06:00 |
|
Ross Thompson
|
16abe90a0d
|
Reduced seladr to 1 bit as second bit is same as selflush.
|
2022-02-11 22:41:36 -06:00 |
|
Ross Thompson
|
b11e9eca7b
|
Reduced complexity of the address selection during flush.
|
2022-02-11 22:27:27 -06:00 |
|
Ross Thompson
|
1255e82154
|
Removed redundant signals from cache.
|
2022-02-11 22:23:47 -06:00 |
|
Ross Thompson
|
52894a7a4f
|
Cache fsm simplifications.
|
2022-02-11 15:16:45 -06:00 |
|
Ross Thompson
|
e2e0a4f595
|
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
|
2022-02-11 15:09:00 -06:00 |
|
Ross Thompson
|
0f2ac0cb24
|
Simplified cache fsm.
|
2022-02-11 14:54:57 -06:00 |
|
Ross Thompson
|
1c83914662
|
Fixed bug.
It was possible for DTLBMissM to prevent a dcache flush.
|
2022-02-11 14:00:01 -06:00 |
|
David Harris
|
de5e80696d
|
Cleaned up synthesis warnings
|
2022-02-11 01:15:16 +00:00 |
|
Ross Thompson
|
5fd22caed4
|
Replacement policy cleanup.
|
2022-02-10 11:42:40 -06:00 |
|
Ross Thompson
|
f716cce832
|
Replacement policy cleanup.
|
2022-02-10 11:40:10 -06:00 |
|
Ross Thompson
|
fdb4f909fc
|
Cleanup + critical path optimizations.
|
2022-02-10 11:11:16 -06:00 |
|
Ross Thompson
|
88c7a94aa9
|
Cache name clarifications.
|
2022-02-10 10:50:17 -06:00 |
|
Ross Thompson
|
32eee5a06a
|
More cache cleanup.
|
2022-02-10 10:43:37 -06:00 |
|
Ross Thompson
|
91f2b5adf5
|
structural muxes.
|
2022-02-09 19:36:21 -06:00 |
|