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289 Commits

Author SHA1 Message Date
Kip Macsai-Goren
985c20c961 updated tests to use the combined library 2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
91915a808c Began to merge test-lib and test-macros into one file 2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
d47a731bda updated verify to only use comments with "#" 2022-02-15 17:06:16 +00:00
Ross Thompson
038897f448 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:47:15 -06:00
David Harris
64e9f4c0d3 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00
bbracker
23b743206a refactor buildroot-config-src into linux folder 2022-02-08 00:26:06 +00:00
bbracker
77e78363cc trim away unneeded linker and header files intended for non-spike machines from wally-riscv-arch-test 2022-02-07 23:59:47 +00:00
David Harris
50b44b4416 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-07 14:43:31 +00:00
Kip Macsai-Goren
ddc8883ea5 fixed verify step to work correctly with comments. clarified copy references without simulating 2022-02-06 19:48:23 +00:00
Kip Macsai-Goren
0eb280b314 added new tests to make and testbench 2022-02-06 19:47:22 +00:00
Kip Macsai-Goren
5d1a0f3402 clarified csr write test 2022-02-06 19:46:29 +00:00
Kip Macsai-Goren
5ddcb29129 added CSR permission tests 2022-02-06 19:45:58 +00:00
Kip Macsai-Goren
51355abc2d light cleanup 2022-02-06 02:05:59 +00:00
Kip Macsai-Goren
07c806b02e added comments to existing MMU tests 2022-02-06 02:05:59 +00:00
Kip Macsai-Goren
e0ed4c00fc added commenting in reference outputs that aren't simulated in spike 2022-02-06 02:05:59 +00:00
Kip Macsai-Goren
1a5111fb75 Allowed commenting in signature files 2022-02-06 02:05:59 +00:00
David Harris
9b55848ffc Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
bbracker
71a0d96c8d Remove rv32e tests from rv32i_m Makefrag so that make XLEN=32 works 2022-02-05 21:34:50 +00:00
David Harris
2c67f32b97 RV32e tests 2022-02-04 14:30:36 +00:00
David Harris
c2ddb121a0 Added E tests to repo 2022-02-03 23:42:31 +00:00
David Harris
17277775e6 E tests 2022-02-03 22:55:55 +00:00
David Harris
4ba37d5cc0 Config file & wally-riscv-arch-test cleanup 2022-02-02 16:35:52 +00:00
Ross Thompson
85d510e315 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-01 10:50:38 -06:00
Ross Thompson
73edd50120 Updated fpga's bootloader to reflect the changes to the gpio address change. 2022-02-01 10:43:24 -06:00
Kip Macsai-Goren
4b94cf9a43 Renamed test library 2022-01-31 20:11:21 +00:00
Kip Macsai-Goren
4d951923f4 updated minfo test to account for no mconfigptr 2022-01-31 20:11:21 +00:00
Kip Macsai-Goren
14933a7231 fixed CSR read-only test to have correct output 2022-01-31 20:11:21 +00:00
Kip Macsai-Goren
242b27705d added machine info test that uses new test library 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
3c61d6eec2 tentatively remade test lib to use macros for more flexibility 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
ee982c7588 converted library to header file for RISCV test compliance 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
9e3b25c940 updated tests to use test title instead of number encoding 2022-01-31 05:54:42 +00:00
David Harris
448acedd8b Set up rv32emc config 2022-01-27 14:37:58 +00:00
Ross Thompson
25c8c45a70 Added generated source code for the wally riscv arch tests rv32i_m and rv64i_m. 2022-01-27 08:11:46 -06:00
David Harris
b359499820 Adjusted test cases for new GPIO base address 2022-01-26 19:15:48 +00:00
David Harris
21bdce63ff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
David Harris
e16982aeb0 New testgen.py 2022-01-26 17:21:02 +00:00
kaveh Pezeshki
b0cbe9dba8 added qemu patches in tests/linux-testgen/qemu 2022-01-24 07:52:07 +00:00
David Harris
43abf25417 moved fp to tests 2022-01-14 23:05:59 +00:00
David Harris
ae6792e354 Moved fp tests from testbench to tests/fp 2022-01-14 23:00:46 +00:00
Kip Macsai-Goren
c251144460 Fixed PMA regions, Added passing PMA tests to regression 2022-01-10 22:08:26 +00:00
Kip Macsai-Goren
54aab6cdde comment cleanup 2022-01-09 18:16:42 +00:00
Kip Macsai-Goren
53ea1360ce updated PMA tests, everything passes except successful writes to protected regions. 2022-01-09 18:16:00 +00:00
Kip Macsai-Goren
5f7323f25f changed test case types to lookup table instead of beq's 2022-01-09 16:56:37 +00:00
David Harris
55e757db03 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 18:10:32 +00:00
David Harris
c9aa21d5a3 FPU debug and configurable logic cleanup 2022-01-06 18:10:25 +00:00
Kip Macsai-Goren
1556fb967d fixed 32 vs 64 bit copying error 2022-01-05 23:14:12 +00:00
Kip Macsai-Goren
172b6190f4 updated pma tests for simpler test lib 2022-01-05 22:10:12 +00:00
Kip Macsai-Goren
bf062e2ed7 updated tests to make correctly with output verification 2022-01-05 21:43:15 +00:00
Kip Macsai-Goren
4efe6813dd allowed option for tests to make without spike simulation. added postverify back in for outputs 2022-01-05 21:17:54 +00:00
Kip Macsai-Goren
1a9de1fae5 updated pma tests to match simpler test library. They don't pass regression yet 2022-01-05 21:13:40 +00:00
Kip Macsai-Goren
0ee4e03cd6 fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh. 2022-01-04 21:30:38 +00:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
David Harris
9693110857 Started adding asynchronous TIMECLK for CLINT 2022-01-02 21:18:16 +00:00
David Harris
d7653dedee Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion 2021-12-30 17:22:18 +00:00
David Harris
9ab4ecdd16 Fixed page table entreis so WALLY-MMU-SV32, SV39, SV48 now run 2021-12-30 16:46:19 +00:00
David Harris
f9ab193ca8 Added partially working MMU tests 2021-12-29 03:14:16 +00:00
David Harris
6e20d011d5 Fixed imperas C tests 2021-12-26 04:45:06 +00:00
Ross Thompson
596cc4fde4 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. 
mv qemu patches to tests directory.
 2021-12-19 20:11:32 -06:00
Ross Thompson
a871118116 Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
23194c0308 fix parseState.py to correctly take in PMPCFG 2021-11-24 16:52:51 -08:00
bbracker
cf27cc7fcd increase niceness of automatic checkpoint generation 2021-11-20 12:48:23 -08:00
David Harris
690410721d Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
8e8b84f532 vert "Simplifying riscv-coremark" 
This reverts commit ce8232e396.
 2021-11-18 18:40:13 -08:00
David Harris
ce8232e396 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
402b473dbb CoreMark testing 2021-11-18 16:14:25 -08:00
David Harris
c610be25a7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
2203590f9f get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
David Harris
570f24a9e4 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
bbracker
e4da379340 genCheckpoint path bugfix 2021-11-06 15:25:10 -07:00
bbracker
9f2a583590 automated checkpoint generator 2021-11-06 14:37:49 -07:00
bbracker
97403af403 update tvLinker to new shared dir 2021-11-06 14:15:16 -07:00
bbracker
8c926dcfd2 make genCheckpoint accept instr count as argument 2021-11-06 14:14:15 -07:00
bbracker
bc6332a780 fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
17e776f853 checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
bbracker
9fe8820ed0 genCheckpoint syntax fix 2021-11-01 15:31:38 -07:00
bbracker
526aff54a8 linux testgen refactor 2021-11-01 14:09:49 -07:00
David Harris
0cc71f1dec added some missing files 2021-11-01 13:36:07 -07:00
David Harris
d449795b3e simplified header and footer 2021-11-01 13:24:18 -07:00
David Harris
d7f0abca5a Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
dda035891a PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
60573b92b2 Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
David Harris
247f247ad3 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
14b9b8126e rearranging testgen 2021-10-29 22:28:37 -07:00
David Harris
67adc1d7d5 removed referenc outputs 2021-10-26 08:51:49 -07:00
Ross Thompson
81054d9168 Fixed issue with dtim (fpga) external abhlite select not triggering. 
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
 2021-10-25 14:51:54 -05:00
David Harris
0dabb6ebd4 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
Ross Thompson
de4ea16d32 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
David Harris
23b3d7dbc1 Move tests into subdirectory and moved wavedrom out of project 2021-10-20 09:03:21 -07:00