forked from Github_Repos/cvw
Began to merge test-lib and test-macros into one file
This commit is contained in:
Kip Macsai-Goren
parent
d47a731bda
commit
91915a808c
@ -22,8 +22,19 @@
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-64.h"
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// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions
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// Ideally this should mean that a test can be written by simply adding .8byte statements as below.
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INIT_TESTS
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s_file_begin:
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j test_loop_setup // begin test loop/table tests instead of executing inline code.
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INIT_TEST_TABLE
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TEST_STACK_AND_DATA
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# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook
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.align 3
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test_cases:
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# ---------------------------------------------------------------------------------------------
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# Test Contents
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@ -39,7 +50,6 @@
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#
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# ---------------------------------------------------------------------------------------------
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# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook
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# =========== test 12.3.1.1 Page Table Translation ===========
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@ -23,6 +23,9 @@
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#include "model_test.h"
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#include "arch_test.h"
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.macro INIT_TESTS
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RVTEST_ISA("RV64I")
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.section .text.init
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@ -56,9 +59,9 @@ RVTEST_CODE_BEGIN
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li a1, 0
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li a2, 0 // reset trap handler inputs to zero
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// go to first test!
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j test_setup
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// go to beginning of S file where we can decide between using the test data loop
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// or using the macro inline code insertion
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j s_file_begin
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// ---------------------------------------------------------------------------------------------
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// General traps Handler
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@ -230,6 +233,9 @@ instrfault:
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ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page)
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j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
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illegalinstr:
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j trapreturn // return to the code after recording the mcause
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accessfault:
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// *** What do I have to do here?
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j trapreturn
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@ -243,7 +249,7 @@ accessfault:
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trap_handler_vector_table:
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.8byte segfault // 0: instruction address misaligned
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.8byte instrfault // 1: instruction access fault
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.8byte segfault // 2: illegal instruction
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.8byte illegalinstr // 2: illegal instruction
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.8byte segfault // 3: breakpoint
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.8byte segfault // 4: load address misaligned
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.8byte accessfault // 5: load access fault
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@ -265,6 +271,249 @@ trap_return_pagetype_table:
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.8byte 0x1E // 2: gigapage has 30 offset bits
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.8byte 0x27 // 3: terapage has 39 offset bits
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.endm
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// Test Summary table!
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// Test Name : Description : Fault output value : Normal output values
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// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------
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// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None
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// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None
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// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None
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// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None
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// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
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// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
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// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
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// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
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// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111)
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// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
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// goto_baremetal : satp.MODE = bare metal : None : None
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// goto_sv39 : satp.MODE = sv39 : None : None
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// goto_sv48 : satp.MODE = sv48 : None : None
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// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
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// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
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// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
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// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR
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// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11
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// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value
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.macro WRITE64 ADDR VAL
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// attempt to write VAL to ADDR
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// Success outputs:
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// None
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// Fault outputs:
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// 0x6: misaligned address
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// 0x7: access fault
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// 0xf: page fault
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li x29, \VAL
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li x30, \ADDR
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sd x29, 0(x30)
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.endm
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.macro WRITE32 ADDR VAL
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// all write tests have the same description/outputs as write64
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li x29, \VAL
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li x30, \ADDR
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sw x29, 0(x30)
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.endm
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.macro WRITE16 ADDR VAL
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// all write tests have the same description/outputs as write64
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li x29, \VAL
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li x30, \ADDR
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sh x29, 0(x30)
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.endm
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.macro WRITE08 ADDR VAL
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// all write tests have the same description/outputs as write64
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li x29, \VAL
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li x30, \ADDR
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sb x29, 0(x30)
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.endm
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.macro READ64 ADDR
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// Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value
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// Success outputs:
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// value read out from ADDR
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// Fault outputs:
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// One of the following followed by 0xBAD
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// 0x4: misaligned address
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// 0x5: access fault
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// 0xD: page fault
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li x7, 0xBAD // bad value that will be overwritten on good reads.
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li x29, \ADDR
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ld x7, 0(x29)
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sd x7, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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.macro READ32 ADDR
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// All reads have the same description/outputs as read64.
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// They will store the sign extended value of what was read out at ADDR
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li x7, 0xBAD // bad value that will be overwritten on good reads.
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li x29, \ADDR
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lw x7, 0(x29)
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sd x7, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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.macro READ16 ADDR
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// All reads have the same description/outputs as read64.
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// They will store the sign extended value of what was read out at ADDR
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li x7, 0xBAD // bad value that will be overwritten on good reads.
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li x29, \ADDR
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lh x7, 0(x29)
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sd x7, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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.macro READ08 ADDR
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// All reads have the same description/outputs as read64.
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// They will store the sign extended value of what was read out at ADDR
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li x7, 0xBAD // bad value that will be overwritten on good reads.
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li x29, \ADDR
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lb x7, 0(x29)
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sd x7, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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// These goto_x_mode tests all involve invoking the trap handler,
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// So their outputs are inevitably:
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// 0x8: test called from U mode
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// 0x9: test called from S mode
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// 0xB: test called from M mode
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// they generally do not fault or cause issues as long as these modes are enabled
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// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
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.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE
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li a0, 2 // determine trap handler behavior (go to machine mode)
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li a1, \RETURN_VPN // return VPN
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li a2, \RETURN_PAGETYPE // return page types
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ecall // writes mcause to the output.
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// now in S mode
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.endm
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.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE
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li a0, 3 // determine trap handler behavior (go to supervisor mode)
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li a1, \RETURN_VPN // return VPN
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li a2, \RETURN_PAGETYPE // return page types
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ecall // writes mcause to the output.
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// now in S mode
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.endm
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.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE
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li a0, 4 // determine trap handler behavior (go to user mode)
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li a1, \RETURN_VPN // return VPN
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li a2, \RETURN_PAGETYPE // return page types
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ecall // writes mcause to the output.
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// now in S mode
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.endm
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// These tests change virtual memory settings, turning it on/off and changing between types.
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// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy?
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.macro GOTO_BAREMETAL
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// Turn translation off
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li x7, 0 // satp.MODE value for bare metal (0)
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slli x7, x7, 60
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li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
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add x7, x7, x28
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csrw satp, x7
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sfence.vma x0, x0 // *** flushes global pte's as well
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.endm
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.macro GOTO_SV39
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// Turn on sv39 virtual memory
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li x7, 8 // satp.MODE value for Sv39 (8)
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slli x7, x7, 60
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li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
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add x7, x7, x28
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csrw satp, x7
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sfence.vma x0, x0 // *** flushes global pte's as well
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.endm
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.macro GOTO_SV48
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// Turn on sv48 virtual memory
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li x7, 9 // satp.MODE value for Sv39 (8)
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slli x7, x7, 60
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li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
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add x7, x7, x28
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csrw satp, x7
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sfence.vma x0, x0 // *** flushes global pte's as well
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.endm
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.macro WRITE_READ_CSR CSR VAL
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// attempt to write CSR with VAL. Note: this also tests read access to CSR
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// Success outputs:
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// value read back out from CSR after writing
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// Fault outputs:
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// The previous CSR value before write attempt
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// *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
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li x30, 0xbad // load bad value to be overwritten by csrr
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li x29, \VAL
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csrw \CSR\(), x29
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csrr x30, \CSR
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sd x30, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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.macro CSR_R_ACCESS CSR
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// verify that a csr is accessible to read but not to write
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// Success outputs:
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// 0x2, then
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// 0x11 *** consider changing to something more meaningful
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// Fault outputs:
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// 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault?
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csrr x29, \CSR
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csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR
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csrr x30, \CSR
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bne x30, x29, 1f // 1f represents write_access
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li x30, 0x11 // Write failed, confirming read only permissions.
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j 2f // j r_access_end
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1: // w_access (write succeeded, violating read-only)
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li x30, 0xBAD
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2: // r_access end
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sd x30, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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.macro EXECUTE_AT_ADDRESS ADDR
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// Execute the code already written to ADDR, returning the value in x7.
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// *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR
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// Assumes the code modifies x7, usually to become 0x111.
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// Sample code: 0x11100393 (li x7, 0x111), 0x00008067 (ret)
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// Success outputs:
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// modified value of x7. (0x111 if you use the sample code)
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// Fault outputs:
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// One of the following followed by 0xBAD
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// 0x0: misaligned address
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// 0x1: access fault
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// 0xC: page fault
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fence.i // forces caches and main memory to sync so execution code written to ADDR can run.
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li x7, 0xBAD
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li x28, \ADDR
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jalr x28 // jump to executable test code
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sd x7, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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.macro END_TESTS
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// invokes one final ecall to return to machine mode then terminates this program, so the output is
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// 0x8: termination called from U mode
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// 0x9: termination called from S mode
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// 0xB: termination called from M mode
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j terminate_test
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.endm
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// ---------------------------------------------------------------------------------------------
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// Test Handler
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//
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@ -284,7 +533,9 @@ trap_return_pagetype_table:
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//
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// ------------------------------------------------------------------------------------------------------------------------------------
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test_setup:
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.macro INIT_TEST_TABLE // *** Consider renaming this test. to what???
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test_loop_setup:
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la x5, test_cases
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test_loop:
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@ -463,6 +714,7 @@ write_pmpcfg_end:
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j test_loop
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write_pmpaddr_0:
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// write_read_csr pmpaddr0, x29
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// writes the value in x29 to the pmpaddr register specified in x28.
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// then writes the final value of pmpaddrX to the output.
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li x7, 0x0
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@ -577,6 +829,10 @@ executable_test:
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addi x16, x16, 8
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j test_loop
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.endm
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// notably, terminate_test is not a part of the test table macro because it needs to be defined
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// in any type of test, macro or test table, for the trap handler to work
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terminate_test:
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li a0, 2 // Trap handler behavior (go to machine mode)
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@ -586,6 +842,8 @@ terminate_test:
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RVTEST_CODE_END
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RVMODEL_HALT
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.macro TEST_STACK_AND_DATA
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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@ -619,6 +877,4 @@ gpr_save:
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#endif
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.align 3
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test_cases:
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.endm
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@ -21,17 +21,19 @@
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-MACROS-64.h"
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#include "WALLY-TEST-LIB-64.h"
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INIT_TESTS
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s_file_begin:
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// Test 5.2.3.1: testing Read-only access to Machine info CSRs
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CSR_R_ACCESS mvendorid
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CSR_R_ACCESS marchid
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CSR_R_ACCESS mimpid
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CSR_R_ACCESS mhartid
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# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22
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csr_r_access mvendorid
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csr_r_access marchid
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csr_r_access mimpid
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csr_r_access mhartid
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# csr_r_access mconfigptr # Unimplemented in spike as of 31 Jan 22
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END_TESTS
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END_TESTS
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TEST_STACK_AND_DATA
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