Noah Boorstin
a4dad3403e
same but do that right this time
2021-04-28 14:27:28 -04:00
Domenico Ottolia
18ecea4506
Make privileged makefiles actually execute tests when you say they should (compile-only is still default)
2021-04-27 23:09:01 -04:00
Domenico Ottolia
60dc6aaf48
Modify make file to make privileged tests always pass Imperas (for testing interrupts) & Add mtvec/stvec tests
2021-04-27 21:47:38 -04:00
Noah Boorstin
44606b6c19
busybear: respect branch predictor disable config
2021-04-27 15:52:18 -04:00
Ross Thompson
8ae28e7887
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-26 14:28:09 -05:00
Ross Thompson
72363f5c66
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Noah Boorstin
ff1a6b63ed
ok but do that better
2021-04-26 14:38:05 -04:00
Noah Boorstin
0324329ed9
linux: start using internal branch predictor signal
2021-04-26 14:34:38 -04:00
Ross Thompson
afbb100860
Fixed issue with not saving the first cache block read on a miss spill.
2021-04-26 12:57:34 -05:00
Noah Boorstin
ee628e388a
minor busybear fixes
2021-04-26 13:24:39 -04:00
Noah Boorstin
0850c18cb7
minor parsing updates
2021-04-26 13:11:01 -04:00
Ross Thompson
8e5409af66
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
Ross Thompson
467a463c13
Reverted back the exe2memfile.pl script changes. Something I changed broke the load tests.
2021-04-26 10:44:27 -05:00
bbracker
31a0387136
merge cleanup; mem init is broken
2021-04-26 08:00:17 -04:00
bbracker
ba94fa3436
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
1cc0dcc83f
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
6e803b724e
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Noah Boorstin
4f8ec22d7f
buildroot: change to new image
2021-04-25 15:15:14 -04:00
Noah Boorstin
42fea2322e
busybear: hopefully last parser changes of the semester
2021-04-25 14:08:18 -04:00
Noah Boorstin
a6f81f5dc0
parsing scripts update
2021-04-24 21:56:16 -04:00
bbracker
86946266cf
thomas fixed it before I did
2021-04-24 09:38:52 -04:00
bbracker
a3487a9e47
do script refactor
2021-04-24 09:32:09 -04:00
Thomas Fleming
c21bd8a463
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-23 20:12:27 -04:00
Thomas Fleming
e3672ca23f
Add address translation to busybear testbench
2021-04-23 20:12:20 -04:00
Thomas Fleming
288a6d82ce
Fix HSIZE and HBURST signal widths in PMA checker
2021-04-23 20:11:43 -04:00
David Harris
85eb6bcf1a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-23 19:04:29 -04:00
David Harris
9415e00bfa
Fixed exe2memfile.pl to handle large files
2021-04-23 19:04:16 -04:00
Ross Thompson
27ef10df07
almost working icache.
2021-04-23 16:47:23 -05:00
Noah Boorstin
09755251bc
busybear
2021-04-23 17:32:37 -04:00
Shriya Nadgauda
5b41ae6a2e
pipeline testing additonal files
2021-04-23 15:46:02 -04:00
Shriya Nadgauda
c66e63ff70
adding pipeline testing
2021-04-23 14:19:17 -04:00
Jarred Allen
c91f1e197b
Remind people to run make allclean when a regression fails
2021-04-22 19:21:00 -04:00
Ross Thompson
020fb65adf
Fixed icache for 32 bit.
...
Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
c42399bdb5
Yes. The hack to not repeat the d memory operation fixed this issue.
2021-04-22 15:22:56 -05:00
Thomas Fleming
da76b80991
Write PCM to TVAL registers
2021-04-22 16:17:57 -04:00
Thomas Fleming
8fee3b3872
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 15:37:19 -04:00
Thomas Fleming
00ce24e67c
Prepare to squash bad ahb accesses
2021-04-22 15:36:45 -04:00
Thomas Fleming
53c05d6a73
Clean up lint errors in fpu and muldiv
...
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
2021-04-22 15:36:03 -04:00
Domenico Ottolia
6b4d2e9634
Fix misa synthesis bug (for real now)
2021-04-22 15:35:20 -04:00
Thomas Fleming
38236e9172
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
73d9e7775c
Pass lint-wally arguments to verilator
2021-04-22 13:39:20 -04:00
Jarred Allen
5df6be3ad5
Add buildroot to regression test
2021-04-22 13:34:56 -04:00
Thomas Fleming
6d1a6694a8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 13:20:12 -04:00
Thomas Fleming
6acaa313b5
Temporarily disable rv64 mmu test
...
Will restore once cache revamp is pushed
2021-04-22 13:19:18 -04:00
Noah Boorstin
3a9eae4244
small parser fix
2021-04-22 12:06:54 -04:00
bbracker
74b35ac57a
greatly improved PLIC register interface
2021-04-22 11:22:01 -04:00
Ross Thompson
d8ab7a5de2
Partially working icache.
...
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Thomas Fleming
00b3e36b30
Refactor tlb_ram to use flop primitives
2021-04-22 01:52:43 -04:00
Thomas Fleming
ef80176e2c
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Domenico Ottolia
fb8f244dab
Fix misa bug
2021-04-22 00:59:07 -04:00
