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Configurable RISC-V Processor
629 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
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Other 4.2%
53c05d6a73
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Thomas Fleming 53c05d6a73 Clean up lint errors in fpu and muldiv 
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
2021-04-22 15:36:03 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Clean up lint errors in fpu and muldiv 2021-04-22 15:36:03 -04:00
.gitignore buildroot parser: more updates 2021-04-17 17:44:46 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor