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Configurable RISC-V Processor
622 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
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Thomas Fleming 00b3e36b30 Refactor tlb_ram to use flop primitives
2021-04-22 01:52:43 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Refactor tlb_ram to use flop primitives 2021-04-22 01:52:43 -04:00
.gitignore buildroot parser: more updates 2021-04-17 17:44:46 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor