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623 Commits

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Author SHA1 Message Date
bbracker
a3487a9e47 do script refactor 2021-04-24 09:32:09 -04:00
Noah Boorstin
3a9eae4244 small parser fix 2021-04-22 12:06:54 -04:00
bbracker
74b35ac57a greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
Domenico Ottolia
fb8f244dab Fix misa bug 2021-04-22 00:59:07 -04:00
Thomas Fleming
e336fbd108 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-04-21 20:01:08 -04:00
Thomas Fleming
4bae666fa1 Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Teo Ene
c7a21b05f7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-21 16:06:33 -05:00
Teo Ene
ddc98e7d08 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Noah Boorstin
cd7ea29ce6 buildroot: add workaround for weird initial MSTATUS state 2021-04-21 16:03:42 -04:00
Domenico Ottolia
44da1488ff Add tests for stval and mtval 2021-04-21 02:31:32 -04:00
Domenico Ottolia
f63f16f486 Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file 2021-04-21 01:12:55 -04:00
Domenico Ottolia
bf86a809eb Add tests for sepc register 2021-04-20 23:50:53 -04:00
Domenico Ottolia
0c307d2db1 Fix synthesis warnings for privileged unit (replace 'initial' settings) 2021-04-20 17:57:56 -04:00
Noah Boorstin
14d28902a8 really small parser update 2021-04-19 23:17:37 -04:00
Noah Boorstin
3f0ead9d4e yay buildroot passes a decent amount of tests now 
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
 2021-04-19 03:26:08 -04:00
Katherine Parry
d12eb0f4eb fixed synth bugs in fpu 2021-04-19 00:39:16 +00:00
Noah Boorstin
2af4e2f4ac slowly more buildroot progress 2021-04-18 18:18:07 -04:00
Noah Boorstin
9bb1233433 neat verilog thing 2021-04-18 17:48:51 -04:00
Noah Boorstin
0fa32ae5d6 buildroot parser: more updates 
5 -> 23 instructions!
 2021-04-17 17:44:46 -04:00
Noah Boorstin
6954e6df4c buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Noah Boorstin
4f97e9e761 start to add buildroot testbench 
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
 2021-04-16 23:27:29 -04:00
Noah Boorstin
b533d17ed8 busybear testgen updates 
and start working on qemu parser
 2021-04-16 15:34:55 -04:00
bbracker
290b3424e5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
9f13ee3f31 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
92bb38fa8c Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Domenico Ottolia
eb9e1843fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 16:57:27 -04:00
Domenico Ottolia
531423d7e1 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Teo Ene
2814579f30 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 15:29:09 -05:00
Teo Ene
374a93dae6 Quick fix to ahblite missing default statement done in class :) 2021-04-15 15:29:04 -05:00
Thomas Fleming
e780694ee0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/mmu/priority_encoder.sv
 2021-04-15 16:20:43 -04:00
Thomas Fleming
6dd7591ceb Change priority encoder to avoid extra assignment 2021-04-15 16:17:35 -04:00
Teo Ene
e3deb49b75 Small update to synth scripts 
Writes out corrent timing reports
 2021-04-15 14:24:39 -05:00
Domenico Ottolia
aa74b14314 Fix bug in device/rv32p/Makefile.include so that 32-bit privileged tests will run 2021-04-15 14:50:03 -04:00
Thomas Fleming
ff9f1e5e72 Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Teo Ene
ad86295fcf Temporary change to mmu/priority_encoder.sv 
Necessary to get synth working
Original HDL is still there, just commented out
 2021-04-15 13:37:12 -05:00
Katherine Parry
636e2de9df integraded the FMA into the FPU 2021-04-15 18:28:00 +00:00
Ross Thompson
87b716170c Merge branch 'bpfixes' into main 2021-04-15 09:06:21 -05:00
Shreya Sanghai
0369fc5d1e Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
ShreyaSanghai
6d4042e479 added localHistoryPredictor 2021-04-15 08:58:22 -05:00
Shreya Sanghai
7e9a0602ea fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
bbracker
e69cc0d23a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 09:06:03 -04:00
bbracker
51cdff3e9b csri lint improvement 2021-04-15 09:05:53 -04:00
David Harris
be07768fbb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-14 23:41:23 -04:00
David Harris
8c1ef5f36c Deleted extraneous exe2memfile.pl 2021-04-14 23:41:15 -04:00
Thomas Fleming
3c49fd08f6 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
bbracker
8f7ddcfdff rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
d66fcbc4ab busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
c75455cc41 busybear testbench updates 
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
 2021-04-14 00:00:27 -04:00
Thomas Fleming
7d2d6823f1 Fix mmu lint errors 2021-04-13 19:19:58 -04:00