slmnemo
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a32698811d
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Updated reference file for UART test
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2022-07-26 09:39:31 -07:00 |
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slmnemo
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528dfd9170
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Committing changes made to UART test
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2022-07-26 09:14:40 -07:00 |
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slmnemo
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5b71ceac5c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 17:13:38 -07:00 |
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slmnemo
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0bfc3fda1b
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Fixed UART FIFO bugs and added FIFO tests
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2022-07-22 17:13:19 -07:00 |
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Daniel Torres
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e02c67ed5e
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fixed 32priv tests, now passing
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2022-07-22 15:35:20 -07:00 |
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Daniel Torres
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d95b266d49
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changes to test.vh for compatability
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2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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2bbfd67082
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added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
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slmnemo
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840c40a7ab
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UART updates and PMA fix
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2022-07-22 14:49:03 -07:00 |
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slmnemo
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6d8988f71f
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Added test comments to reference output
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2022-07-22 12:35:59 -07:00 |
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Daniel Torres
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5d7171f6f8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
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526f70e772
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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slmnemo
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12c92a05ff
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Added new PLIC and UART tests
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2022-07-22 07:12:55 -07:00 |
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slmnemo
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49565f944c
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Added PLIC and UART tests and new functions to the test library
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2022-07-22 07:10:39 -07:00 |
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slmnemo
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77f7b179ee
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fixed GPIO test by adding a new function to clear PLIC interrupts
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2022-07-19 08:59:16 -07:00 |
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slmnemo
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43549b10fb
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Fixed error in gpio test
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2022-07-08 02:27:16 -07:00 |
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Katherine Parry
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0b40f38f02
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added load and store test
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2022-07-07 21:48:51 +00:00 |
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slmnemo
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b3cd9de9e8
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Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests.
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2022-07-05 18:21:17 -07:00 |
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slmnemo
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5ef1266d76
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Added termination line to CLINT test
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2022-06-27 20:16:29 -07:00 |
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slmnemo
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448c9fdbb9
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Add CLINT tests from book
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2022-06-27 20:09:58 -07:00 |
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slmnemo
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ddf757078b
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Added reset read testcodes to GPIO
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2022-06-27 18:56:35 -07:00 |
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slmnemo
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4c8f5fbd89
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Fixed error in GPIO signature
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2022-06-23 14:12:28 -07:00 |
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David Harris
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66b148b76e
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GPIO tests
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2022-06-23 21:06:11 +00:00 |
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slmnemo
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3d794742e9
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Updating new GPIO tests
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2022-06-23 13:22:00 -07:00 |
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slmnemo
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2b2760f5bd
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-21 02:16:26 -07:00 |
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slmnemo
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2b2ddbcc5e
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Added rudimentary GPIO test according to testplans in chapter 15
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2022-06-21 02:16:21 -07:00 |
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Katherine Parry
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254ebf478e
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added fld in rv32 - needs testing
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2022-06-20 22:53:13 +00:00 |
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DTowersM
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13c1cf12b2
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added some comments to help debuggers in the future
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2022-06-10 01:44:52 +00:00 |
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DTowersM
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dd34f25ffd
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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Kip Macsai-Goren
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94cb6caec6
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Fixed priv test reference outputs to have the right number of "DEADBEEF"s (1024)
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2022-05-12 22:30:14 +00:00 |
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David Harris
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aa452b2f38
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Moved some privileged tests to be simulated.
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2022-05-12 04:45:41 +00:00 |
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David Harris
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9b7aab122e
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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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2022-05-05 14:37:21 +00:00 |
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Kip Macsai-Goren
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7249879a74
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clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals
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2022-05-04 23:01:23 +00:00 |
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Kip Macsai-Goren
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99423993a9
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added explicit clears to mstatus.mie
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2022-05-04 23:00:17 +00:00 |
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Kip Macsai-Goren
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536df2b8ad
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Updated test libraries to reflect variable name changes
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2022-05-04 21:39:36 +00:00 |
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Kip Macsai-Goren
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35e619ae74
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renamed test_loop_setup to run_test_loop
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2022-05-04 21:39:09 +00:00 |
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Kip Macsai-Goren
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26dfe36c16
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renamed debug to extended signature
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2022-05-04 21:38:37 +00:00 |
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Kip Macsai-Goren
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895a4f4832
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updated makefrag and tests.vh to reflect removed tests, new names
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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a9a434fced
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removed fp-diabled test and leftover mimpid test
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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f36fdf940d
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removed instruction misaligned tests from trap tests, signatures
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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badbe0840f
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renamed all tests to have lower-case titles except for WALLY
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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64ba550493
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general test cleanup of comments and old files
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2022-04-29 19:55:29 +00:00 |
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Kip Macsai-Goren
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36f5624255
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re-renamed status-mie-s to status-sie
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2022-04-29 19:55:13 +00:00 |
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Kip Macsai-Goren
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75e90f193e
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added missing SIE test
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2022-04-29 19:54:29 +00:00 |
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Kip Macsai-Goren
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407cdfbab7
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renamed registers in test library to RISC-V ABI name rater than x2, etc..
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2022-04-29 18:52:42 +00:00 |
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Kip Macsai-Goren
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c0b56bfd27
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renamed PIE-stack tests to status-mie for clarity
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2022-04-29 18:30:39 +00:00 |
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Kip Macsai-Goren
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2f17edb5f4
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added missing output for sret
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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aedf0341af
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added 32 bit versions of new tests. all but timeout wait pass regression
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2022-04-28 18:14:07 +00:00 |
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Kip Macsai-Goren
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e0a1a54678
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added floating point instructions to privileged tests
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2022-04-25 17:47:10 +00:00 |
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Kip Macsai-Goren
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08d4c29724
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Removed test cases irrelevant to this implementation, added explanatory comments.
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2022-04-22 23:06:52 +00:00 |
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Kip Macsai-Goren
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abfbbaccba
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Added testing for every bit field in MIE, rather than just one
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2022-04-22 23:05:54 +00:00 |
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