Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,260 Commits 14 Branches 1 Tag 31 MiB
9de97c1e20
Commit Graph

1260 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
David Harris
9de97c1e20 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
David Harris
2ba82d1a5c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:26:51 -04:00
David Harris
223086ac33 added or.sv 2021-07-13 13:26:40 -04:00
Katherine Parry
ca19b2e215 Fixed writting MStatus FS bits 2021-07-13 13:22:04 -04:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
David Harris
93d6688c3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:19:24 -04:00
David Harris
b5dddec858 Fixed InstrValid from W to M stage for CSR performance counters 2021-07-13 13:19:13 -04:00
bbracker
3565580f40 updated buildroot make procedure to incorporate configs more robustly 2021-07-13 12:40:14 -04:00
bbracker
99587f58f7 whoops I accidentally made main.config into a symbolic link; now it is a source file 2021-07-13 11:00:01 -04:00
bbracker
fab906821a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 10:04:13 -04:00
bbracker
4b615c1564 working config for a buildroot that boots 2021-07-13 10:04:09 -04:00
David Harris
861ef5e1cb Replaced .or with or_rows structural code in MMU read circuitry for synthesis. 2021-07-13 09:32:02 -04:00
Katherine Parry
f3ac46df86 fcvt.sv cleanup 2021-07-11 21:30:01 -04:00
Katherine Parry
36f59f3c99 Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
bbracker
6bd0ca673c rootfs.cpio no longer overlaps 2021-07-11 05:11:12 -04:00
bbracker
feaeeaf6ac greatly stripped down unused stuff in linux config 2021-07-10 11:53:35 -04:00
David Harris
20f2a4e47c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 19:18:35 -04:00
David Harris
d3ab6b192a added missing tlbmixer.sv 2021-07-09 19:18:23 -04:00
bbracker
3be73695e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 18:56:28 -04:00
bbracker
2a54f6f242 fix_mem.py bugfix 2021-07-09 18:56:17 -04:00
bbracker
1f52a2f938 organize/update buildroot scripts for new image 2021-07-09 17:03:47 -04:00
David Harris
39bd7e7edc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 07:53:30 -04:00
David Harris
5c2f774c35 Simplified tlbmixer mux to and-or 2021-07-08 23:34:24 -04:00
David Harris
74b6d13195 Fixed missing stall in InstrRet counter 2021-07-08 20:08:04 -04:00
bbracker
44a48cf28d organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files 2021-07-08 19:18:11 -04:00
David Harris
4f1a85ca7c Eliminate reserved bits from TLB RAM 2021-07-08 17:35:00 -04:00
David Harris
38772de21f Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram 2021-07-08 16:58:11 -04:00
David Harris
1190729896 TLB cleanup to match diagrams 2021-07-08 16:52:06 -04:00
David Harris
5d5274ec73 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-07 06:32:29 -04:00
David Harris
2bab3f769b Renamed tlb ReadLines to Matches 2021-07-07 06:32:26 -04:00
Abe
84711fbdc8 Updated MISA defining as well as porting sizes for peripherals (34 to 56) 2021-07-07 02:37:09 -04:00
Abe
c721341691 Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time. 2021-07-07 02:28:11 -04:00
Abe
b536065ee8 Removed debugging loop to test timers for clarity 2021-07-06 23:37:43 -04:00
Abe
8dc40e988e Updated portme file to include counters MTIME and MINSTRET. Timer currently set to read milliseconds running at 100MHZ, but this can be changed by setting a different clock speed in the testbench sv file and manipulating TIMER_RES_DIVIDER on line 120 2021-07-06 23:35:47 -04:00
Abe
b757c96b2d Changed SvMode to SVMode on line 76 2021-07-06 23:28:58 -04:00
David Harris
af619dcd75 Added ASID matching for CAM 2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
8350622f65 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 18:54:41 -04:00
David Harris
7d857cf4bd more TLB name touchups 2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
e08a578908 fixed upper bits page fault signal 2021-07-06 18:32:47 -04:00
David Harris
2e2aa2a972 connected signals in tlb by name instead of .* 2021-07-06 17:22:10 -04:00
David Harris
ee3a321002 changed tlbphysicalpagemask to structural 2021-07-06 17:16:58 -04:00
David Harris
f960561cbb changed tlbphysicalpagemask to structural 2021-07-06 17:08:04 -04:00
David Harris
fd0cd930a7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 15:29:49 -04:00
David Harris
032c38b7e7 MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB 2021-07-06 15:29:42 -04:00
Kip Macsai-Goren
757e4f3b54 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 15:05:51 -04:00
Ross Thompson
412691df2d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 13:45:20 -05:00
Ross Thompson
3345ed7ff4 Merged several of the load/store/instruction access faults inside the mmu. 
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
 2021-07-06 13:43:53 -05:00
bbracker
d3dd70e3e6 more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
Kip Macsai-Goren
137145144f edited tests so regression would pass with float enabled. this IS NOT a comprehensive test for fs yet 2021-07-06 14:28:26 -04:00
Abe
8854532a79 Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140) 2021-07-06 12:37:58 -04:00