Ross Thompson
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9d03109f34
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Officially added global history with speculation to types of branch predictors.
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2023-01-05 14:04:09 -06:00 |
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Ross Thompson
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0737efc86c
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More branch predictor cleanup.
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2023-01-05 13:36:51 -06:00 |
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Ross Thompson
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808c106504
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Two bit predictor cleanup.
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2023-01-05 13:27:22 -06:00 |
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Ross Thompson
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14ebf2360d
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Simplified gshare.
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2023-01-04 23:51:09 -06:00 |
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Ross Thompson
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0eceeeeeaa
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Simiplified global history branch predictor.
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2023-01-04 23:41:55 -06:00 |
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davidharrishmc
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4a2ed0142f
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Update decompress.sv
typo
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2023-01-04 17:01:26 -08:00 |
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Ross Thompson
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872ff619e3
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Fixed problems with changes to ram2p.
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2022-12-29 17:13:48 -06:00 |
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Ross Thompson
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3f4b3a4159
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Added about moving decompressed config generate.
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2022-12-27 15:04:55 -06:00 |
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Ross Thompson
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4f436dc7f0
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Added missing assignment for no branch predictor mode.
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2022-12-24 17:08:29 -06:00 |
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Ross Thompson
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a2de53aeeb
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
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2022-12-23 15:10:37 -06:00 |
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Ross Thompson
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2cc4d66ded
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Renamed IFU and LSU stalls.
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2022-12-22 21:56:33 -06:00 |
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Ross Thompson
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3b791b768a
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Success we've replaced TrapM with FlushD in the IFU.
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2022-12-22 21:36:49 -06:00 |
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Ross Thompson
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e0e92952c3
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Partial cleanup for BP.
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2022-12-22 20:33:38 -06:00 |
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Ross Thompson
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206bc7daa6
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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Ross Thompson
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41fe876e7a
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First pass at resolving ifu flush on trap rather than FlushD.
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2022-12-22 15:53:06 -06:00 |
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Ross Thompson
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e7a44d8975
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Changed GatedStallF to GatedStallD.
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2022-12-21 16:12:55 -06:00 |
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Ross Thompson
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91f948a91c
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The optimzied PC+2/4 logic still hanges on wally32priv.
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2022-12-21 09:19:34 -06:00 |
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Ross Thompson
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6858b7568c
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Renamed PCPlusUpperF to PCPlus4F.
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2022-12-21 09:18:30 -06:00 |
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Ross Thompson
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ac94b55e74
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Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
Switched to even simplier PC+2/4 logic.
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2022-12-21 09:00:09 -06:00 |
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Ross Thompson
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fe723af1af
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Comments about PC+2/4.
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2022-12-21 08:35:43 -06:00 |
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Ross Thompson
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f860440361
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-20 18:09:37 -06:00 |
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Ross Thompson
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97593e8a6f
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Moved privileged pc logic into privileged unit.
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2022-12-20 17:55:45 -06:00 |
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David Harris
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8f640f050f
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IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI
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2022-12-20 15:38:30 -08:00 |
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Ross Thompson
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35ad49502f
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Implement FENCE.I as NOP when ZIFENCEI is not supported.
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2022-12-20 17:34:11 -06:00 |
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David Harris
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f3e9950317
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-20 14:43:33 -08:00 |
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David Harris
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e7702e48b7
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FPU remove unused signals
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2022-12-20 14:43:30 -08:00 |
|
Ross Thompson
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8029b12f2a
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Renumbered bits for PCPlusUpper.
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2022-12-20 16:33:49 -06:00 |
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Ross Thompson
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c4901450c4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-20 12:58:59 -06:00 |
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Ross Thompson
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684d260005
|
Reorganized IFU PCNextF logic.
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2022-12-20 12:58:54 -06:00 |
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David Harris
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e74d47bcb4
|
Renamed renamed sram to ram
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2022-12-20 08:36:45 -08:00 |
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David Harris
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54e856c4f5
|
Renamed SRAM2P1R1W to lower case
|
2022-12-20 02:09:36 -08:00 |
|
Ross Thompson
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dedc08bd42
|
several options for pcnextf on fence.i
|
2022-12-19 23:33:12 -06:00 |
|
Ross Thompson
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2df18cc758
|
More bp/ifu pcmux cleanup.
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2022-12-19 23:16:58 -06:00 |
|
Ross Thompson
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565585b35a
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Moved more muxes inside bp.
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2022-12-19 22:51:55 -06:00 |
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Ross Thompson
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d8ee0ea59d
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Begin cleanup of ifu. partial move of pc muxes inside bp.
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2022-12-19 22:46:11 -06:00 |
|
David Harris
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9fea16fd20
|
Simplified InstrRawD register
|
2022-12-19 15:18:42 -08:00 |
|
Ross Thompson
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e774dd2db9
|
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
|
2022-12-15 09:53:35 -06:00 |
|
Ross Thompson
|
0716aedbd5
|
Removed unused flushf.
|
2022-12-11 16:28:11 -06:00 |
|
Ross Thompson
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115e9e7bb3
|
Renamed CPUBusy to GatedStallF in IFU.
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2022-12-11 15:54:19 -06:00 |
|
Ross Thompson
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c50a2bd8bf
|
Changed CPUBusy to Stall in ebu modules.
|
2022-12-11 15:51:35 -06:00 |
|
Ross Thompson
|
3ddf509f28
|
Renamed CPUBusy to Stall in cache.
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2022-12-11 15:49:34 -06:00 |
|
Ross Thompson
|
1463e9b1d4
|
Finished merge of kip and ross's ifu fix.
|
2022-12-09 16:52:22 -06:00 |
|
Ross Thompson
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6f01ea12e8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-09 16:42:16 -06:00 |
|
Kip Macsai-Goren
|
f486a763d9
|
Addded fix for 32 bit periph test and added test to regression
|
2022-12-06 09:56:08 -08:00 |
|
Ross Thompson
|
9ee2d84c7c
|
Fixed bug Kip found.
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
|
2022-12-06 10:37:45 -06:00 |
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Ross Thompson
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ac0f6ddb7b
|
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
|
2022-11-16 15:38:37 -06:00 |
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Ross Thompson
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f03d5d3ac8
|
Renamed Flush to FlushStage in the cache.
|
2022-11-14 14:11:05 -06:00 |
|
Ross Thompson
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1a00e7bbee
|
Changed names of cache signals.
|
2022-11-13 21:36:12 -06:00 |
|
Ross Thompson
|
90697ef888
|
Moved all remaining bus logic from the LSU into ahbcacheinterface.
|
2022-11-11 14:30:32 -06:00 |
|
Ross Thompson
|
31d5eabd77
|
Renamed Word to Beat for ahbcacheinterface.
|
2022-11-09 17:52:50 -06:00 |
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