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98e93a63c0
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390 Commits

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Author SHA1 Message Date
bbracker
98e93a63c0 maybe AHB works now 2021-03-18 17:47:00 -04:00
Jarred Allen
e69376c823 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
4fd0ecff69 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
7446a7b479 fix to last commit 2021-03-17 15:07:02 -05:00
Teo Ene
3e849f99a6 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
d72d774a0b addition to last commit 2021-03-17 14:52:31 -05:00
Teo Ene
dfe6df2e00 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
041439c008 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
d0ddb5f461 replicating coremark changes into coremark bare 2021-03-17 14:36:34 -04:00
Elizabeth Hedenberg
da758e9e14 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
f070aae847 Fixed issue with sim-wally-batch. Are people still using this script? 2021-03-17 11:17:52 -05:00
Ross Thompson
3618a39087 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
9f8f0242ca Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Domenico Ottolia
487b198055 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-16 23:27:09 -04:00
Domenico Ottolia
748372dc45 Add test runner for privileged 2021-03-16 23:26:59 -04:00
Noah Boorstin
bfa7aedd35 busybear: add seperate message on bad memory access becasue its confusing 2021-03-16 21:42:26 -04:00
Noah Boorstin
e7fae21eb8 busybear: add COUNTERS define 2021-03-16 21:08:47 -04:00
Domenico Ottolia
d354cbd37d Add privileged testbench 2021-03-16 20:28:38 -04:00
Domenico Ottolia
82ea97e304 Add privileged tests for mcause 2021-03-16 19:22:36 -04:00
Domenico Ottolia
1ceb7a7431 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-16 19:12:21 -04:00
Domenico Ottolia
8b0c57a511 Add new make privileged command 2021-03-16 19:11:58 -04:00
Jarred Allen
152ffd16e2 Undo accidental change 2021-03-16 18:16:00 -04:00
Jarred Allen
ae5417195a Condense the parallel and non-parallel wally-pipelined-batch.do files into one 2021-03-16 18:15:13 -04:00
Jarred Allen
f6cbe44cbd Change busybear to only check that first 100k instructions load 2021-03-16 17:43:39 -04:00
Jarred Allen
a82aa23399 Fix icache for jumping into misaligned instructions 2021-03-16 16:57:51 -04:00
Domenico Ottolia
b2faf3c888 Add privileged tests folder 2021-03-16 16:11:20 -04:00
Jarred Allen
2d2092e8ab Merge remote-tracking branch 'origin/main' into cache 2021-03-16 14:17:39 -04:00
Shreya Sanghai
74f1641c5a Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
Jarred Allen
36452749d7 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Noah Boorstin
9e1612c166 remove regression-wally.sh 2021-03-15 19:03:57 -04:00
Noah Boorstin
400791163e copy Ross's branch predictor preload change into busybear 2021-03-15 18:27:27 -04:00
Ross Thompson
4c8952de6a Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Ross Thompson
f2a6e8c6cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
The last commit message about rv32ic having issues is now invalid. Looks like the issue was resolved.
 2021-03-15 12:06:18 -05:00
Ross Thompson
806cfc4ea5 Fixed the parallel script so the rv64ic passes. 
rv32ic and busybear still have issues.
 2021-03-15 12:04:59 -05:00
Jarred Allen
ac9fd5a323 Fix BEQZ tests 2021-03-14 15:42:27 -04:00
Jarred Allen
926235b180 Merge upstream changes 2021-03-14 14:57:53 -04:00
Jarred Allen
deb13f34bb Get non-jump case working 2021-03-14 14:46:21 -04:00
bbracker
e58d17d5b7 slightly smarter dtim HREADY 2021-03-13 07:03:33 -05:00
bbracker
345254b5a3 slightly smarter dtim HREADY 2021-03-13 06:55:34 -05:00
bbracker
c5015e5809 imem rd2 adrbits bugfix 2021-03-13 00:10:41 -05:00
Ross Thompson
940d892f29 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 20:18:35 -06:00
Ross Thompson
7ceef2b0c6 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
bbracker
f4fb546969 clint HREADY signal update 2021-03-12 20:23:55 -05:00
Ross Thompson
86078d856f Cleaned up the function radix exractFunctionRadix script. I should change the name as this is no longer a modelsim radix. 2021-03-12 15:29:02 -06:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
7743d8edc3 Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
David Harris
56b690ccb9 Drafted rv32a tests 2021-03-12 00:06:23 -05:00
David Harris
865c103599 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Ross Thompson
318b642359 Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Noah Boorstin
cc94046084 test regression script: add commented out rv32ic tests 2021-03-11 12:57:54 -05:00