Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
337 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
806cfc4ea5
Go to file
Ross Thompson 806cfc4ea5 Fixed the parallel script so the rv64ic passes. 
rv32ic and busybear still have issues.
2021-03-15 12:04:59 -05:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Fixed the parallel script so the rv64ic passes. 2021-03-15 12:04:59 -05:00
.gitignore Added debug option to disable the function radix if not needed. 2021-03-10 15:17:02 -06:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor