Xavi/cvw
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Author SHA1 Message Date
bbracker
cc484569cd fix typo 2021-10-24 15:05:00 -07:00
bbracker
046a78a8fc manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
bbracker
3531a934c9 checkpoint generator bugfix 2021-10-24 14:46:56 -07:00
Ross Thompson
8a51fe76c1 Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
bbracker
c0a7b12f94 or actually needed to reduce expectations of buildroot 2021-10-24 06:59:34 -07:00
bbracker
d3969bb1ba increase regression's expectations of buildroot 2021-10-24 06:50:22 -07:00
bbracker
36b39358c6 add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
bbracker
d445095f1b revamp linux testvector generation for refactoring checkpoint generation 2021-10-24 06:14:11 -07:00
bbracker
e0b6566cbd buildroot do scripts now compile flops 2021-10-23 23:14:59 -07:00
bbracker
26eead1c77 add W stage signals to linux testbench 2021-10-23 14:00:53 -07:00
bbracker
de6a52f6eb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
3c0b0987d2 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
200eb453fb wrapping up lint cleanup; many unused signals removed 2021-10-23 12:15:14 -07:00
David Harris
c9e9cd4a60 more lsu/ifu lint cleanup 2021-10-23 12:10:13 -07:00
David Harris
2cfbd888fd more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
62a23fe878 lsu/ifu lint cleanup 2021-10-23 11:41:20 -07:00
David Harris
61fdb3d902 random lint cleanup 2021-10-23 11:24:36 -07:00
David Harris
8d9efcbafb IEU cleanup 2021-10-23 11:13:28 -07:00
David Harris
4bf823e063 lint cleanup 2021-10-23 11:03:28 -07:00
David Harris
d570df864f IEU lint cleanup 2021-10-23 10:51:53 -07:00
David Harris
8e516e6391 Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
David Harris
33358d101e Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
David Harris
d24bece3a8 Lint cleanup 2021-10-23 09:58:52 -07:00
David Harris
2e796e3da2 lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00
David Harris
c316bff15a subword read and csrc lint cleanup 2021-10-23 09:29:15 -07:00
David Harris
28d8f6d5cf FMA and CSRC lint cleanup 2021-10-23 09:20:24 -07:00
David Harris
11b0607e63 Lint cleanup 2021-10-23 09:06:21 -07:00
David Harris
ac1b1bfbb6 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
0dabb6ebd4 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
David Harris
f483e8002a Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
cbcf6121dc hope I added logic declarations to divconv_pipe ok 2021-10-23 08:10:16 -07:00
James E. Stine
3e1317b8ee Remove redundant logic value 2021-10-23 10:02:47 -05:00
David Harris
e2e950ac0f Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
4c480a40f6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3249d65209 Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
77e2b6f9a9 Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
kipmacsaigoren
2a86a6717d lowered number of paths to speed synth up and removed extra unnecessary report copying. 2021-10-22 15:25:11 -05:00
kipmacsaigoren
ef297067e9 removed reduntant definitions for FPU in MISA. 2021-10-22 15:18:25 -05:00
James E. Stine
f6e8e45901 Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
Katherine Parry
7c7c0f538a put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
James E. Stine
0dcca43f48 Get rid of lint warning - still need more testing though 2021-10-21 15:19:22 -05:00
James E. Stine
dd7dbaa382 Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
bafb3a983d Fix fpdivsqrt lint error on CPA for convergence 2021-10-20 17:46:13 -05:00
Ross Thompson
de4ea16d32 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
Ross Thompson
fe24bc5a43 Added debug signals to dcache. 2021-10-20 15:52:05 -05:00
David Harris
ceaf84a3ce removed .* from wallypipeliendsoc 2021-10-20 13:49:18 -07:00
davidharrishmc
3cdac72e96 Update README.md 2021-10-20 10:49:41 -07:00
kipmacsaigoren
e80fd40258 Fixed path to src and config files, added mdu timing reports 2021-10-20 12:41:14 -05:00
kipmacsaigoren
8ea17c784a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-20 12:15:53 -05:00
kipmacsaigoren
ffacb7ab67 Removed historical outputs from repo 2021-10-20 12:15:40 -05:00