slmnemo
c5c886ddc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:23:20 -08:00
slmnemo
40efffc70b
Removed .*s from muldiv.sv
2021-11-17 13:23:12 -08:00
Noah Limpert
bbd17e730b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:04:33 -08:00
Noah Limpert
70a84b56c8
Updated IFU variable naming for clarity
2021-11-17 12:39:05 -08:00
Kevin Kim
6437c04074
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 12:18:25 -08:00
Kevin Kim
38437c664e
root level makefile added
2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
7a8c21e71f
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Ross Thompson
f4c221f20a
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
slmnemo
86ff349baf
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 10:39:52 -08:00
slmnemo
129b9721d6
Removed .* from muldiv.
2021-11-17 10:39:18 -08:00
Ross Thompson
23e78c4842
Fixed uart by reversing the bit order on transmit.
...
Set prescale to 0.
2021-11-17 10:32:41 -06:00
Skylar Litz
6fde97b16c
fixed interrupt timing bug
2021-11-16 16:46:17 -08:00
davidharrishmc
c9ac0c0769
Update README.md
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updated linux_testvectors path
2021-11-16 12:33:47 -08:00
David Harris
c610be25a7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-16 12:30:55 -08:00
bbracker
2203590f9f
get current privilege level from GDB for checkpoints
2021-11-15 14:49:00 -08:00
Ross Thompson
1c9670d739
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
2021-11-12 17:37:07 -06:00
Ross Thompson
7497422667
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Skylar Litz
3dd83b3113
fix timing of delayed interrupt
2021-11-11 09:35:51 -08:00
David Harris
570f24a9e4
bringing Coremark back to life
2021-11-10 12:43:31 -08:00
kipmacsaigoren
30b08c4281
fixed small errors causing overwrites in timing reports
2021-11-10 13:01:09 -06:00
Kevin Kim
7cb8b76ef6
Makefile added in regression directory:
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-cd's into imperas then runs make commands, finally running the tvLinker script
2021-11-09 10:55:48 -08:00
bbracker
e4da379340
genCheckpoint path bugfix
2021-11-06 15:25:10 -07:00
bbracker
6e67ad9335
update README.md to reflect new tvLinker location
2021-11-06 15:02:16 -07:00
bbracker
f6a555009b
increase expectations for buildroot and timeout count
2021-11-06 14:57:29 -07:00
bbracker
9f2a583590
automated checkpoint generator
2021-11-06 14:37:49 -07:00
bbracker
97403af403
update tvLinker to new shared dir
2021-11-06 14:15:16 -07:00
bbracker
8c926dcfd2
make genCheckpoint accept instr count as argument
2021-11-06 14:14:15 -07:00
bbracker
c92d41a597
checkpoint MIDELEG support
2021-11-06 03:44:23 -07:00
bbracker
bc6332a780
fix merge conflict
2021-11-05 23:42:15 -07:00
bbracker
17e776f853
checkpoints now use binary ram files
2021-11-05 22:37:05 -07:00
kipmacsaigoren
22fe81a34d
changed number of critical paths reported to 1, added lots of internal signals and new report files.
2021-11-05 11:59:33 -05:00
davidharrishmc
331e0f9f6e
fixed 64i
2021-11-03 13:49:07 -07:00
davidharrishmc
5b2816d3a5
fixed 64i
2021-11-03 13:40:23 -07:00
davidharrishmc
3f6b918458
added wally-riscv-arch-test compile commands
2021-11-03 13:30:21 -07:00
Kevin
11efaa2669
changed code aligner to run recursively on a root directory
...
-only runs the aligner on .sv files
-runs recursively on sub-directories
2021-11-03 10:49:34 -07:00
slmnemo
f7642a282d
edited to include missing instructions
...
added cd tests before cd imperas-riscv-tests to reflect new tests folder
modified cd ../addins so we can point to it from the new imperas-riscv-tests within the tests folder
added instructions so the buildroot test exists
2021-11-03 01:50:00 -07:00
slmnemo
68d9702b1b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-03 00:50:27 -07:00
bbracker
0c7681b942
fix testbench interrupt timing
2021-11-02 21:19:12 -07:00
bbracker
9fe8820ed0
genCheckpoint syntax fix
2021-11-01 15:31:38 -07:00
bbracker
526aff54a8
linux testgen refactor
2021-11-01 14:09:49 -07:00
David Harris
0cc71f1dec
added some missing files
2021-11-01 13:36:07 -07:00
David Harris
d449795b3e
simplified header and footer
2021-11-01 13:24:18 -07:00
David Harris
d7f0abca5a
Add3d wally32i test
2021-11-01 13:17:49 -07:00
David Harris
dda035891a
PIPELINE test running
2021-11-01 12:44:35 -07:00
David Harris
60573b92b2
Adding custom Wally test infrastructure
2021-11-01 08:48:46 -07:00
bbracker
fe2cda493c
fix buildroot graphical sim
2021-10-31 18:33:43 -07:00
davidharrishmc
db8d5d58e4
Added instructions for rv64i_m/D
2021-10-30 07:34:53 -07:00
David Harris
360930fe8b
Fixed exe2memfile parsing of weird line in arch64d test
2021-10-30 07:26:18 -07:00
David Harris
bd1a4769ab
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-29 22:32:08 -07:00
David Harris
247f247ad3
tesgen cleanup, added riscv-arch-test D tests
2021-10-29 22:31:48 -07:00
