Ross Thompson
89a30e7e37
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
9ebea891e2
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
731fbfc851
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
b462554896
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
dacba855da
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
Ross Thompson
09dcb56217
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
3ddf509f28
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
9806babe9e
Renamed SelBusBuffer to SelFetchBuffer.
2022-12-05 17:51:13 -06:00
Ross Thompson
2bcaacb179
Cache signal renames.
2022-12-04 16:09:09 -06:00
Ross Thompson
cb310bfb1d
Removed unused port on cacheway.
2022-12-01 11:47:48 -06:00
Ross Thompson
5e5cca6ae1
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
2022-11-30 11:01:25 -06:00
Ross Thompson
ed54959378
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
f03d5d3ac8
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
42c0a10d07
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
98d4929c57
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
Ross Thompson
f9a04c13df
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
92d7be645b
Reordered the eviction and fetch in cache so it follows a more logical order.
2022-10-04 17:36:07 -05:00
Ross Thompson
afc6934249
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
dfe6bdd06d
Found a hidden bug in the cache to bus fsm interlock.
2022-09-26 17:41:30 -05:00
Ross Thompson
fd2a8e621a
Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
2022-09-26 12:48:26 -05:00
Ross Thompson
dcc00ef4b3
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
2ae62c2869
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
5b8f888e21
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
a532eb61ba
Progress.
2022-08-30 14:17:00 -05:00
Ross Thompson
21526957cf
Updated fpga test bench.
...
Solved read delay cache bug. Introduced during cache optimizations.
2022-08-21 15:59:54 -05:00
Ross Thompson
92c3cdc27d
Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
2022-08-21 15:28:29 -05:00
Ross Thompson
96d6218078
Possible reduction of ignorerequest.
2022-08-19 18:07:44 -05:00
Ross Thompson
334008630f
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
2022-07-24 01:20:29 -05:00
Ross Thompson
856ac24686
Removed replay from the config files.
2022-07-24 00:34:11 -05:00
Ross Thompson
458bfbf6f6
Merged evict dirty clear with flush write back.
2022-07-24 00:22:43 -05:00
Ross Thompson
7d026e02f2
cache cleanup after removing replay on cpubusy.
2022-07-22 23:30:25 -05:00
Ross Thompson
706bc819e1
cache fsm cleanup after removal of replay.
2022-07-22 23:25:09 -05:00
Ross Thompson
0f586c9ed3
Possible improvement to cache which removes the cpu_busy states.
2022-07-22 23:20:37 -05:00
Ross Thompson
9868e685a4
Minor cleanup of cache.
2022-07-19 23:04:23 -05:00
Ross Thompson
6c8ac7851e
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
2022-07-19 22:42:25 -05:00
Ross Thompson
ffda64587c
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
2022-07-18 23:37:18 -05:00
Ross Thompson
396f697d2f
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
7b96b3f73c
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec
More cache cleanup.
2022-02-13 12:38:39 -06:00
Ross Thompson
dd944265aa
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
bf173b035c
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
David Harris
de5e80696d
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
