forked from Github_Repos/cvw
259 lines
13 KiB
Systemverilog
259 lines
13 KiB
Systemverilog
///////////////////////////////////////////
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// dcache (data cache) fsm
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//
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// Written: ross1728@gmail.com August 25, 2021
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// Implements the L1 data cache fsm
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//
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// Purpose: Controller for the dcache fsm
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cachefsm
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(input logic clk,
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input logic reset,
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// inputs from IEU
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input logic [1:0] RW,
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input logic [1:0] Atomic,
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input logic FlushCache,
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// hazard inputs
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input logic CPUBusy,
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// interlock fsm
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input logic IgnoreRequestTLB,
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input logic IgnoreRequestTrapM,
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// Bus inputs
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input logic CacheBusAck,
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// dcache internals
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input logic CacheHit,
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input logic VictimDirty,
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input logic FlushAdrFlag,
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input logic FlushWayFlag,
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// hazard outputs
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output logic CacheStall,
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// counter outputs
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output logic CacheMiss,
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output logic CacheAccess,
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// Bus outputs
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output logic CacheCommitted,
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output logic CacheWriteLine,
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output logic CacheFetchLine,
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// dcache internals
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output logic [1:0] SelAdr,
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output logic SetValid,
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output logic ClearValid,
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output logic SetDirty,
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output logic ClearDirty,
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output logic FSMWordWriteEn,
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output logic FSMLineWriteEn,
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output logic SelEvict,
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output logic LRUWriteEn,
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output logic SelFlush,
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output logic FlushAdrCntEn,
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output logic FlushWayCntEn,
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output logic FlushAdrCntRst,
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output logic FlushWayCntRst,
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output logic save,
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output logic restore);
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logic [1:0] PreSelAdr;
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logic resetDelay;
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logic AMO;
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logic DoAMO, DoRead, DoWrite, DoFlush;
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logic DoAMOHit, DoReadHit, DoWriteHit, DoAnyHit;
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logic DoAMOMiss, DoReadMiss, DoWriteMiss, DoAnyMiss;
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logic FlushFlag, FlushWayAndNotAdrFlag;
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typedef enum logic [3:0] {STATE_READY,
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STATE_MISS_FETCH_WDV,
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STATE_MISS_FETCH_DONE,
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STATE_MISS_EVICT_DIRTY,
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STATE_MISS_WRITE_CACHE_LINE,
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STATE_MISS_READ_WORD,
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STATE_MISS_READ_WORD_DELAY,
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STATE_MISS_WRITE_WORD,
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STATE_CPU_BUSY,
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STATE_FLUSH,
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STATE_FLUSH_CHECK,
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STATE_FLUSH_INCR,
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STATE_FLUSH_WRITE_BACK,
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STATE_FLUSH_CLEAR_DIRTY} statetype;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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logic IgnoreRequest;
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assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM;
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// if the command is used in the READY state then the cache needs to be able to supress
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// using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB.
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// need to re organize all of these. Low priority though.
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assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation.
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assign AMO = Atomic[1] & (&RW);
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assign DoAMO = AMO & ~IgnoreRequest;
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assign DoAMOHit = DoAMO & CacheHit;
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assign DoAMOMiss = DoAMO & ~CacheHit;
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assign DoRead = RW[1] & ~IgnoreRequest;
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assign DoReadHit = DoRead & CacheHit;
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assign DoReadMiss = DoRead & ~CacheHit;
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assign DoWrite = RW[0] & ~IgnoreRequest;
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assign DoWriteHit = DoWrite & CacheHit;
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assign DoWriteMiss = DoWrite & ~CacheHit;
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assign DoAnyMiss = DoAMOMiss | DoReadMiss | DoWriteMiss;
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assign DoAnyHit = DoAMOHit | DoReadHit | DoWriteHit;
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assign FlushFlag = FlushAdrFlag & FlushWayFlag;
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// outputs for the performance counters.
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assign CacheAccess = (DoAMO | DoRead | DoWrite) & CurrState == STATE_READY;
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assign CacheMiss = CacheAccess & ~CacheHit;
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// special case on reset. When the fsm first exists reset the
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// PCNextF will no longer be pointing to the correct address.
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// But PCF will be the reset vector.
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flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
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assign SelAdr = resetDelay ? 2'b01 : PreSelAdr;
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always_ff @(posedge clk)
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if (reset) CurrState <= #1 STATE_READY;
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else CurrState <= #1 NextState;
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always_comb begin
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NextState = STATE_READY;
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case (CurrState)
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STATE_READY: if(IgnoreRequest) NextState = STATE_READY;
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else if(DoFlush) NextState = STATE_FLUSH;
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else if(DoAMOHit & CPUBusy) NextState = STATE_CPU_BUSY; // change
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else if(DoReadHit & CPUBusy) NextState = STATE_CPU_BUSY;
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else if(DoWriteHit & CPUBusy) NextState = STATE_CPU_BUSY;
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else if(DoReadMiss | DoWriteMiss | DoAMOMiss) NextState = STATE_MISS_FETCH_WDV; // change
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else NextState = STATE_READY;
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STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE;
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else NextState = STATE_MISS_FETCH_WDV;
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STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
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else NextState = STATE_MISS_WRITE_CACHE_LINE;
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STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD;
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STATE_MISS_READ_WORD: if (RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD;
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else NextState = STATE_MISS_READ_WORD_DELAY;
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STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY;
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else if(CPUBusy) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
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else NextState = STATE_MISS_EVICT_DIRTY;
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STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
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STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK;
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else if (FlushFlag) NextState = STATE_READY;
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else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
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else NextState = STATE_FLUSH_CHECK;
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STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK;
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STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY;
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else NextState = STATE_FLUSH_WRITE_BACK;
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STATE_FLUSH_CLEAR_DIRTY: if(FlushAdrFlag & FlushWayFlag) NextState = STATE_READY;
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else if (FlushWayFlag) NextState = STATE_FLUSH_INCR;
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else NextState = STATE_FLUSH_CHECK;
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default: NextState = STATE_READY;
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endcase
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end
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// com back to CPU
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assign CacheCommitted = CurrState != STATE_READY;
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assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAnyMiss)) |
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_MISS_FETCH_DONE) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
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(CurrState == STATE_MISS_READ_WORD) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_FLUSH) |
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(CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) |
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(CurrState == STATE_FLUSH_INCR) |
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(CurrState == STATE_FLUSH_WRITE_BACK) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
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// write enables internal to cache
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assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
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assign ClearValid = '0;
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assign SetDirty = (CurrState == STATE_READY & DoAMO) |
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(CurrState == STATE_READY & DoWrite) |
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(CurrState == STATE_MISS_READ_WORD_DELAY & AMO) |
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(CurrState == STATE_MISS_WRITE_WORD);
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assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY);
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assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) |
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(CurrState == STATE_MISS_READ_WORD_DELAY & AMO) |
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(CurrState == STATE_MISS_WRITE_WORD);
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assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE);
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assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) |
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(CurrState == STATE_MISS_READ_WORD_DELAY) |
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(CurrState == STATE_MISS_WRITE_WORD);
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// Flush and eviction controls
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assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY);
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assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
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(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY);
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assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag;
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assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayAndNotAdrFlag) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayAndNotAdrFlag);
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assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
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assign FlushAdrCntRst = (CurrState == STATE_READY);
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assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
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// Bus interface controls
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assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss);
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assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) |
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(CurrState == STATE_FLUSH_CHECK & VictimDirty);
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// handle cpu stall.
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assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY;
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assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) |
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(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | RW[1]) & CPUBusy) |
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(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
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// **** can this be simplified?
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assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss.
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(CurrState == STATE_READY & (AMO & CacheHit)) |
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(CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) |
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(CurrState == STATE_READY & (RW[0] & CacheHit)) |
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_MISS_FETCH_DONE) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
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(CurrState == STATE_MISS_READ_WORD) |
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(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) |
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(CurrState == STATE_MISS_WRITE_WORD) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY))) ? 2'b01 :
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((CurrState == STATE_FLUSH) |
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(CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) |
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(CurrState == STATE_FLUSH_INCR) |
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(CurrState == STATE_FLUSH_WRITE_BACK) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag))) ? 2'b10 :
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2'b00;
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endmodule // cachefsm
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