Katherine Parry
6c4aa624a5
fpu cleanup
2021-07-24 15:00:56 -04:00
Katherine Parry
ef28679721
fpu cleanup
2021-07-24 14:59:57 -04:00
Kip Macsai-Goren
3008111bcd
added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet
2021-07-23 16:02:42 -04:00
Kip Macsai-Goren
381a93b45b
added sfence to legal instructions, zeroed out rom file to populate for tests
2021-07-23 15:55:08 -04:00
Kip Macsai-Goren
221b8097d6
uppdated makefile to not simulate pmp/pma tests with ovpsim
2021-07-23 15:29:03 -04:00
Kip Macsai-Goren
63f8a97939
fixed write pmp csr test, added physical exe test, fixed instr fault return problem, general light cleanup
2021-07-23 15:27:54 -04:00
Kip Macsai-Goren
da9ead2d95
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-23 15:16:01 -04:00
bbracker
b093bf84a4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-23 14:00:52 -04:00
bbracker
0e64b99dc0
testbench workaround for QEMU's SSTATUS XLEN bits
2021-07-23 14:00:44 -04:00
kipmacsaigoren
f3579032bd
Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's
2021-07-23 11:57:58 -05:00
David Harris
5d2b30e332
Removed LEVELx states from HPTW
2021-07-23 08:11:15 -04:00
Ross Thompson
9939c66a1f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 19:42:32 -05:00
Ross Thompson
3e916da36e
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
...
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
Kip Macsai-Goren
52faa22774
include SFENCE.VMA in legal instructions
2021-07-22 20:24:24 -04:00
Kip Macsai-Goren
5faae637ce
removed backups that are no longer needed
2021-07-22 20:23:17 -04:00
David Harris
98660e0d19
Minor unpacking cleanup
2021-07-22 17:52:37 -04:00
Ross Thompson
551e3491af
Moved the ReadDataW register into the datapath.
...
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
fbbfc799b9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 14:05:08 -05:00
Ross Thompson
9c90b4bdf7
Fixed bug with the itlb fault not dcache ptw ready state to ready state.
2021-07-22 14:04:56 -05:00
David Harris
c9890afb7f
Move Z sign swapping out of unpacker
2021-07-22 14:32:38 -04:00
David Harris
31be570461
Move Z=0 mux out of unpacker.
2021-07-22 14:28:55 -04:00
David Harris
63718cef8f
Move Z=0 mux out of unpacker.
2021-07-22 14:22:28 -04:00
David Harris
21a65f45cd
Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.
2021-07-22 14:18:27 -04:00
David Harris
b53eb6d030
Simplify unpacker
2021-07-22 13:42:16 -04:00
David Harris
19dac66264
Simplify unpacker
2021-07-22 13:40:42 -04:00
David Harris
44141047ef
Removed Assumed1 from FPU interface
2021-07-22 13:04:47 -04:00
David Harris
3ad2170ffd
Simplified interface to fclassify and fsgn (fixed)
2021-07-22 12:33:38 -04:00
David Harris
5e155e4fd1
Simplified interface to fclassify and fsgn
2021-07-22 12:30:46 -04:00
Ross Thompson
b4029a2848
Cleaned up icache and dcache.
2021-07-22 11:06:44 -05:00
Ross Thompson
3dd89a7e62
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 10:38:24 -05:00
Ross Thompson
25a8920a69
Tested all numbers of ways for dcache 1, 2, 4, and 8.
2021-07-22 10:38:07 -05:00
bbracker
d3059dd04c
fix UART RX FIFO bug where tail pointer can overtake head pointer
2021-07-22 02:09:41 -04:00
bbracker
57a2917997
make address translator signals visible in waveview
2021-07-21 20:07:49 -04:00
bbracker
cca16cc5b4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-21 20:07:03 -04:00
bbracker
6e460c5032
replace physical address checking with virtual address checking because address translator is broken
2021-07-21 19:47:13 -04:00
bbracker
25391bcfce
hardcoded hack to fix missing STVEC vector
2021-07-21 19:34:57 -04:00
Ross Thompson
dac93bb366
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
c69a5dc8a6
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
71375ba655
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:39:07 -05:00
Ross Thompson
7785401281
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 14:56:30 -05:00
Ross Thompson
313bc5255c
Improved address bus names and usages in the walker, dcache, and tlbs.
...
Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Ross Thompson
310b454fa1
Added comment about better muxing.
2021-07-21 14:40:14 -05:00
Ross Thompson
5860f147d4
4 way set associative is now working.
2021-07-21 14:01:14 -05:00
Kip Macsai-Goren
1c1ae2d61e
removed remaining 32 bit loads/stores with 64 bit ones.
2021-07-21 14:45:22 -04:00
Kip Macsai-Goren
4eaf95de60
Fixed TLB parameterization and valid bit flop to correctly do instr page faults
2021-07-21 14:44:43 -04:00
Katherine Parry
01f0b4e5df
FDIV and FSQRT work
2021-07-21 14:08:14 -04:00
bbracker
f9c0d33773
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-21 13:04:11 -04:00
bbracker
82ce85c24f
progress on recovering from QEMU's errors
2021-07-21 13:00:32 -04:00
Ross Thompson
e0990535e1
Fixed remaining bugs in 2 way set associative dcache.
2021-07-21 10:35:23 -05:00
Ross Thompson
3f780f012a
Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux.
...
Also forgot to include cacheLRU.sv file.
2021-07-20 23:17:42 -05:00
