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86 Commits

Author SHA1 Message Date
Ross Thompson
aeeaf6d919 Progress. 2021-06-24 13:05:22 -05:00
Kip Macsai-Goren
c8f80967a6 added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day. 2021-06-23 19:59:06 -04:00
Ross Thompson
9b8bcb8e57 Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. 
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
 2021-06-23 16:43:22 -05:00
Ross Thompson
f74ecbb81e Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache. 2021-06-23 15:13:56 -05:00
Ross Thompson
f79e5eaa47 Icache now uses physical lenght bits rather than XLEN. 2021-06-21 16:41:09 -05:00
David Harris
5d6dc82db2 Added Physical Address and Size to PMA Checker/MMU 2021-06-21 01:27:02 -04:00
David Harris
1ec90a5e1f Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
Ross Thompson
70c45a5349 Revert "Icache now uses physical lenght bits rather than XLEN." 
This reverts commit 16266d978a.
 2021-06-19 08:58:34 -05:00
Ross Thompson
16266d978a Icache now uses physical lenght bits rather than XLEN. 2021-06-18 12:02:59 -05:00
David Harris
de221ff2d0 Changed physical addresses to PA_BITS in size in MMU and TLB 2021-06-18 09:11:31 -04:00
David Harris
75870a16d7 Restored PCCorrectE declaration in IFU 2021-06-09 21:09:16 -04:00
David Harris
0ffbd03139 More verilator fixes, but bpred is broken 2021-06-09 21:03:03 -04:00
David Harris
90e5781471 Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
Kip Macsai-Goren
d6f47d5917 making mmu branch line up with main 2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
e209dbcf50 some cleanup of signals, not done yet 2021-06-08 13:39:32 -04:00
Kip Macsai-Goren
49200bd922 Cleaned up some unused signals 2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
1ae529c450 restructured so that pma/pmp are a part of mmu 2021-06-04 17:05:07 -04:00
David Harris
a26bf37be8 Started MMU 2021-06-04 11:59:14 -04:00
Ross Thompson
89ad4477e4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 11:33:12 -05:00
bbracker
39ae743543 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
Ross Thompson
8a035104ac It's a bit sloppy, but the global history predictor is working correctly now. 
There were two major bugs with the predictor.
First the update mechanism was completely wrong.  The PHT is updated with the GHR that was used to lookup the prediction.  PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted.  This is important so that back to back branches' GHRs are not the same.  The must be different to avoid aliasing.  Speculation of the GHR update allows them to be different.  On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed.  Updates to follow.
 2021-05-27 23:06:28 -05:00
Ross Thompson
65632cb7c9 Fixed minor bug in instruction class decoding. 2021-05-24 13:41:14 -05:00
Ross Thompson
72f77656a3 Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link). 2021-05-24 12:37:16 -05:00
Ross Thompson
a54c231489 Eliminated extra register and fixed ports to icache. 
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
 2021-05-03 12:04:54 -05:00
Ross Thompson
c0a4b7cb17 Fixed typo in ifu for bypassing branch predictor. 
Fixed missing signal name in local history predictor.
 2021-05-03 08:56:45 -05:00
Ross Thompson
72363f5c66 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
bbracker
31a0387136 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
ba94fa3436 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
1cc0dcc83f progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
6e803b724e Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
Ross Thompson
020fb65adf Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Ross Thompson
d8ab7a5de2 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Thomas Fleming
e336fbd108 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-04-21 20:01:08 -04:00
Thomas Fleming
4bae666fa1 Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Teo Ene
ddc98e7d08 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Ross Thompson
251ece20fe Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Jarred Allen
850f728cc7 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Thomas Fleming
ff9f1e5e72 Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Jarred Allen
fc8b8ad7aa A few more cache fixes 2021-04-13 01:07:40 -04:00
Jarred Allen
d99b8f772e Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
c91436d3b7 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Ross Thompson
9172e52286 Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
2a308309e4 fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
631454ccf9 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00