Kip Macsai-Goren
6a76f40e26
light cleanup
2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
05e944628d
added high bit registers to CSR permission tests
2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
e16581d73d
added CSR permission and minfor to 32 bit tests
2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
943c4d9d7c
merged test macros in with 32 bit tests
2022-02-15 20:19:14 +00:00
David Harris
72e83db9fe
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d3034c4f01
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
f734afb866
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
1326ade1a0
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
David Harris
bf1b02be92
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-15 19:01:42 +00:00
David Harris
8166e07004
Sythesis uncertainty cleanup
2022-02-15 19:01:38 +00:00
Kip Macsai-Goren
9ff4025844
light cleanup for privileged tests
2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
985c20c961
updated tests to use the combined library
2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
91915a808c
Began to merge test-lib and test-macros into one file
2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
d47a731bda
updated verify to only use comments with "#"
2022-02-15 17:06:16 +00:00
David Harris
dee2822359
srt fixes
2022-02-14 18:40:27 +00:00
David Harris
99aacd5aca
srt batch files
2022-02-14 18:37:46 +00:00
ushakya22
f4740cfda4
bring branch back into main
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Merge branch 'srt_division_with_unpacker' into main
2022-02-14 18:25:34 +00:00
ushakya22
4170b54c28
work in progress exponent handling
2022-02-14 18:24:29 +00:00
David Harris
1d5c8a7b98
t push
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
David Harris
e6be19dfad
Improved makefile and synthesis script for parallel processing, max optimization
2022-02-14 01:22:17 +00:00
Ross Thompson
1bb4d46ac1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
e852cb8a31
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
1d7949513d
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec
More cache cleanup.
2022-02-13 12:38:39 -06:00
ushakya22
f87667d120
Added unpacker into testbench for srt
2022-02-12 22:05:18 +00:00
David Harris
0399a63b48
Enbled multicore synthesis
2022-02-12 06:44:58 +00:00
David Harris
b360e7b941
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
a34cbdb7d0
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
Ross Thompson
dd944265aa
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
bf173b035c
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662
Fixed bug.
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It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
33beaa4593
Updates to linux wave.
2022-02-11 13:28:18 -06:00
Ross Thompson
d9f77d3659
Updated linux wave.
2022-02-11 13:15:42 -06:00
Ross Thompson
1a1629c62f
linux wave cleanup.
2022-02-11 10:48:45 -06:00
Ross Thompson
febd019854
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
6d12010d02
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
de5e80696d
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
David Harris
cd243a965f
merged synth.tcl
2022-02-11 00:21:24 +00:00
David Harris
4749941a22
Waive some synthesis warning messages
2022-02-11 00:20:23 +00:00
Ross Thompson
689c32215f
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
James Stine
39fd199538
Slight tweaks to synthDC for library variables
2022-02-10 17:56:27 -06:00
Ross Thompson
39be787821
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-10 17:52:27 -06:00
Ross Thompson
9fb612d4ff
Updated wave files to reflect recent changes.
2022-02-10 17:52:19 -06:00
