forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
bf1b02be92
@ -1483,13 +1483,13 @@ string imperas32f[] = '{
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string wally64priv[] = '{
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`WALLYTEST,
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"rv64i_m/privilege/WALLY-MMU-SV39", "30A0",
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"rv64i_m/privilege/WALLY-MMU-SV48", "30A0",
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"rv64i_m/privilege/WALLY-PMP", "30A0",
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"rv64i_m/privilege/WALLY-PMA", "30A0",
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"rv64i_m/privilege/WALLY-minfo-01", "30A0",
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"rv64i_m/privilege/WALLY-CSR-permission-s-01", "40A0",
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"rv64i_m/privilege/WALLY-CSR-permission-u-01", "40A0"
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"rv64i_m/privilege/WALLY-MMU-SV39", "40A0",
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"rv64i_m/privilege/WALLY-MMU-SV48", "40A0",
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"rv64i_m/privilege/WALLY-PMP", "40A0",
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"rv64i_m/privilege/WALLY-PMA", "40A0",
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"rv64i_m/privilege/WALLY-minfo-01", "40A0",
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"rv64i_m/privilege/WALLY-CSR-permission-s-01", "50A0",
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"rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0"
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};
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string wally64periph[] = '{
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@ -28,15 +28,15 @@ do
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echo -e "Check $(printf %-24s ${stub}) \e[33m ... IGNORE \e[39m"
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continue
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fi
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# KMG: changed diff snippet to a grep that will strip comments with '//' and '#' out of the reference file
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diff --ignore-case --ignore-trailing-space --strip-trailing-cr <(grep -o '^[^//#]*' ${ref}) ${sig} &> /dev/null
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# KMG: changed diff snippet to a grep that will strip comments with '#' out of the reference file
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diff --ignore-case --ignore-trailing-space --strip-trailing-cr <(grep -o '^[^#]*' ${ref}) ${sig} &> /dev/null
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if [ $? == 0 ]
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then
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echo -e "\e[32m ... OK \e[39m"
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else
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echo -e "\e[31m ... FAIL \e[39m"
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FAIL=$((${FAIL} + 1))
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sdiff ${ref} ${sig} > ${dif}
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sdiff <(grep -o '^[^#]*' ${ref}) ${sig} > ${dif}
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fi
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done
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@ -63,9 +63,8 @@ copy:
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$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
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$(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>)
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$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
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$(V) echo "Copying References without simulating for the following tests:"
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$(V) echo $(target_tests_nosim)
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$(V) for test in $(target_tests_nosim); do grep -o '^[^//#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done
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$(V) echo "Copying References without simulating for the following tests: $(target_tests_nosim)"
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$(V) for test in $(target_tests_nosim); do grep -o '^[^#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done
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compile: $(combined_elf)
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run: $(target_log)
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@ -21,133 +21,137 @@
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-MACROS-64.h"
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#include "WALLY-TEST-LIB-64.h"
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INIT_TESTS
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s_file_begin:
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# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
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# *** several of these appear not to be implemented in the assembler?
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# I get "assembler messages: error: unkown CSR" with many of them.
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goto_s_mode 0x0, 0x0
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GOTO_S_MODE 0x0, 0x0
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# Attempt to write 0xbad to each of these CSRs and read the value back
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# should result in an illegal instruction for the write and read, respectively
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# Machine information Registers
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write_read_csr mvendorid, 0xbad
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write_read_csr marchid, 0xbad
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write_read_csr mimpid, 0xbad
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write_read_csr mhartid, 0xbad
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# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
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WRITE_READ_CSR mvendorid, 0xbad
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WRITE_READ_CSR marchid, 0xbad
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WRITE_READ_CSR mimpid, 0xbad
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WRITE_READ_CSR mhartid, 0xbad
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# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
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# Machine Trap Setup
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write_read_csr mstatus, 0xbad
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write_read_csr misa, 0xbad
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write_read_csr medeleg, 0xbad
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write_read_csr mideleg, 0xbad
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write_read_csr mie, 0xbad
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write_read_csr mtvec, 0xbad
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write_read_csr mcounteren, 0xbad
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WRITE_READ_CSR mstatus, 0xbad
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WRITE_READ_CSR misa, 0xbad
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WRITE_READ_CSR medeleg, 0xbad
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WRITE_READ_CSR mideleg, 0xbad
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WRITE_READ_CSR mie, 0xbad
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WRITE_READ_CSR mtvec, 0xbad
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WRITE_READ_CSR mcounteren, 0xbad
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# Machine Trap Handling
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write_read_csr mscratch, 0xbad
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write_read_csr mepc, 0xbad
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write_read_csr mcause, 0xbad
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write_read_csr mtval, 0xbad
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write_read_csr mip, 0xbad
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# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make???
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# write_read_csr mtval2, 0xbad
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WRITE_READ_CSR mscratch, 0xbad
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WRITE_READ_CSR mepc, 0xbad
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WRITE_READ_CSR mcause, 0xbad
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WRITE_READ_CSR mtval, 0xbad
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WRITE_READ_CSR mip, 0xbad
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# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
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# WRITE_READ_CSR mtval2, 0xbad
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# Machine Configuration
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# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
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# write_read_csr mseccgf, 0xbad
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# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
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# WRITE_READ_CSR mseccgf, 0xbad
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# Machine Memory Protection
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write_read_csr pmpcfg0, 0xbad
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write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
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WRITE_READ_CSR pmpcfg0, 0xbad
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WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
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write_read_csr pmpaddr0, 0xbad
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write_read_csr pmpaddr1, 0xbad
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write_read_csr pmpaddr2, 0xbad
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write_read_csr pmpaddr3, 0xbad
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write_read_csr pmpaddr4, 0xbad
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write_read_csr pmpaddr5, 0xbad
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write_read_csr pmpaddr6, 0xbad
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write_read_csr pmpaddr7, 0xbad
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write_read_csr pmpaddr8, 0xbad
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write_read_csr pmpaddr9, 0xbad
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write_read_csr pmpaddr10, 0xbad
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write_read_csr pmpaddr11, 0xbad
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write_read_csr pmpaddr12, 0xbad
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write_read_csr pmpaddr13, 0xbad
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write_read_csr pmpaddr14, 0xbad
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write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
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WRITE_READ_CSR pmpaddr0, 0xbad
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WRITE_READ_CSR pmpaddr1, 0xbad
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WRITE_READ_CSR pmpaddr2, 0xbad
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WRITE_READ_CSR pmpaddr3, 0xbad
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WRITE_READ_CSR pmpaddr4, 0xbad
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WRITE_READ_CSR pmpaddr5, 0xbad
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WRITE_READ_CSR pmpaddr6, 0xbad
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WRITE_READ_CSR pmpaddr7, 0xbad
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WRITE_READ_CSR pmpaddr8, 0xbad
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WRITE_READ_CSR pmpaddr9, 0xbad
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WRITE_READ_CSR pmpaddr10, 0xbad
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WRITE_READ_CSR pmpaddr11, 0xbad
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WRITE_READ_CSR pmpaddr12, 0xbad
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WRITE_READ_CSR pmpaddr13, 0xbad
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WRITE_READ_CSR pmpaddr14, 0xbad
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WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
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# Machine Counter/Timers
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write_read_csr mcycle, 0xbad
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write_read_csr minstret, 0xbad
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write_read_csr mhpmcounter3, 0xbad
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write_read_csr mhpmcounter4, 0xbad
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write_read_csr mhpmcounter5, 0xbad
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write_read_csr mhpmcounter6, 0xbad
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write_read_csr mhpmcounter7, 0xbad
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write_read_csr mhpmcounter8, 0xbad
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write_read_csr mhpmcounter9, 0xbad
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write_read_csr mhpmcounter10, 0xbad
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write_read_csr mhpmcounter11, 0xbad
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write_read_csr mhpmcounter12, 0xbad
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write_read_csr mhpmcounter13, 0xbad
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write_read_csr mhpmcounter14, 0xbad
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write_read_csr mhpmcounter15, 0xbad
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write_read_csr mhpmcounter16, 0xbad
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write_read_csr mhpmcounter17, 0xbad
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write_read_csr mhpmcounter18, 0xbad
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write_read_csr mhpmcounter19, 0xbad
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write_read_csr mhpmcounter20, 0xbad
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write_read_csr mhpmcounter21, 0xbad
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write_read_csr mhpmcounter22, 0xbad
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write_read_csr mhpmcounter23, 0xbad
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write_read_csr mhpmcounter24, 0xbad
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write_read_csr mhpmcounter25, 0xbad
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write_read_csr mhpmcounter26, 0xbad
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write_read_csr mhpmcounter27, 0xbad
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write_read_csr mhpmcounter28, 0xbad
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write_read_csr mhpmcounter29, 0xbad
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write_read_csr mhpmcounter30, 0xbad
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write_read_csr mhpmcounter31, 0xbad
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WRITE_READ_CSR mcycle, 0xbad
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WRITE_READ_CSR minstret, 0xbad
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WRITE_READ_CSR mhpmcounter3, 0xbad
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WRITE_READ_CSR mhpmcounter4, 0xbad
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WRITE_READ_CSR mhpmcounter5, 0xbad
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WRITE_READ_CSR mhpmcounter6, 0xbad
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WRITE_READ_CSR mhpmcounter7, 0xbad
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WRITE_READ_CSR mhpmcounter8, 0xbad
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WRITE_READ_CSR mhpmcounter9, 0xbad
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WRITE_READ_CSR mhpmcounter10, 0xbad
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WRITE_READ_CSR mhpmcounter11, 0xbad
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WRITE_READ_CSR mhpmcounter12, 0xbad
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WRITE_READ_CSR mhpmcounter13, 0xbad
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WRITE_READ_CSR mhpmcounter14, 0xbad
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WRITE_READ_CSR mhpmcounter15, 0xbad
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WRITE_READ_CSR mhpmcounter16, 0xbad
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WRITE_READ_CSR mhpmcounter17, 0xbad
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WRITE_READ_CSR mhpmcounter18, 0xbad
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WRITE_READ_CSR mhpmcounter19, 0xbad
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WRITE_READ_CSR mhpmcounter20, 0xbad
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WRITE_READ_CSR mhpmcounter21, 0xbad
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WRITE_READ_CSR mhpmcounter22, 0xbad
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WRITE_READ_CSR mhpmcounter23, 0xbad
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WRITE_READ_CSR mhpmcounter24, 0xbad
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WRITE_READ_CSR mhpmcounter25, 0xbad
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WRITE_READ_CSR mhpmcounter26, 0xbad
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WRITE_READ_CSR mhpmcounter27, 0xbad
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WRITE_READ_CSR mhpmcounter28, 0xbad
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WRITE_READ_CSR mhpmcounter29, 0xbad
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WRITE_READ_CSR mhpmcounter30, 0xbad
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WRITE_READ_CSR mhpmcounter31, 0xbad
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# Machine Counter Setup
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write_read_csr mcountinhibit, 0xbad
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write_read_csr mhpmevent3, 0xbad
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write_read_csr mhpmevent4, 0xbad
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write_read_csr mhpmevent5, 0xbad
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write_read_csr mhpmevent6, 0xbad
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write_read_csr mhpmevent7, 0xbad
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write_read_csr mhpmevent8, 0xbad
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write_read_csr mhpmevent9, 0xbad
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write_read_csr mhpmevent10, 0xbad
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write_read_csr mhpmevent11, 0xbad
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write_read_csr mhpmevent12, 0xbad
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write_read_csr mhpmevent13, 0xbad
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write_read_csr mhpmevent14, 0xbad
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write_read_csr mhpmevent15, 0xbad
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write_read_csr mhpmevent16, 0xbad
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write_read_csr mhpmevent17, 0xbad
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write_read_csr mhpmevent18, 0xbad
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write_read_csr mhpmevent19, 0xbad
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write_read_csr mhpmevent20, 0xbad
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write_read_csr mhpmevent21, 0xbad
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write_read_csr mhpmevent22, 0xbad
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write_read_csr mhpmevent23, 0xbad
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write_read_csr mhpmevent24, 0xbad
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write_read_csr mhpmevent25, 0xbad
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||||
write_read_csr mhpmevent26, 0xbad
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write_read_csr mhpmevent27, 0xbad
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write_read_csr mhpmevent28, 0xbad
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||||
write_read_csr mhpmevent29, 0xbad
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write_read_csr mhpmevent30, 0xbad
|
||||
write_read_csr mhpmevent31, 0xbad
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||||
WRITE_READ_CSR mcountinhibit, 0xbad
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||||
WRITE_READ_CSR mhpmevent3, 0xbad
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WRITE_READ_CSR mhpmevent4, 0xbad
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WRITE_READ_CSR mhpmevent5, 0xbad
|
||||
WRITE_READ_CSR mhpmevent6, 0xbad
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||||
WRITE_READ_CSR mhpmevent7, 0xbad
|
||||
WRITE_READ_CSR mhpmevent8, 0xbad
|
||||
WRITE_READ_CSR mhpmevent9, 0xbad
|
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WRITE_READ_CSR mhpmevent10, 0xbad
|
||||
WRITE_READ_CSR mhpmevent11, 0xbad
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||||
WRITE_READ_CSR mhpmevent12, 0xbad
|
||||
WRITE_READ_CSR mhpmevent13, 0xbad
|
||||
WRITE_READ_CSR mhpmevent14, 0xbad
|
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WRITE_READ_CSR mhpmevent15, 0xbad
|
||||
WRITE_READ_CSR mhpmevent16, 0xbad
|
||||
WRITE_READ_CSR mhpmevent17, 0xbad
|
||||
WRITE_READ_CSR mhpmevent18, 0xbad
|
||||
WRITE_READ_CSR mhpmevent19, 0xbad
|
||||
WRITE_READ_CSR mhpmevent20, 0xbad
|
||||
WRITE_READ_CSR mhpmevent21, 0xbad
|
||||
WRITE_READ_CSR mhpmevent22, 0xbad
|
||||
WRITE_READ_CSR mhpmevent23, 0xbad
|
||||
WRITE_READ_CSR mhpmevent24, 0xbad
|
||||
WRITE_READ_CSR mhpmevent25, 0xbad
|
||||
WRITE_READ_CSR mhpmevent26, 0xbad
|
||||
WRITE_READ_CSR mhpmevent27, 0xbad
|
||||
WRITE_READ_CSR mhpmevent28, 0xbad
|
||||
WRITE_READ_CSR mhpmevent29, 0xbad
|
||||
WRITE_READ_CSR mhpmevent30, 0xbad
|
||||
WRITE_READ_CSR mhpmevent31, 0xbad
|
||||
|
||||
END_TESTS
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -21,149 +21,153 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-MACROS-64.h"
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode.
|
||||
|
||||
goto_u_mode 0x0, 0x0
|
||||
GOTO_U_MODE 0x0, 0x0
|
||||
|
||||
# Attempt to write 0xbad to each of these CSRs and read the value back
|
||||
# should result in an illegal instruction for the write and read, respectively
|
||||
|
||||
# Supervisor Trap Setup
|
||||
write_read_csr sstatus, 0xbad
|
||||
write_read_csr sie, 0xbad
|
||||
write_read_csr stvec, 0xbad
|
||||
write_read_csr scounteren, 0xbad
|
||||
WRITE_READ_CSR sstatus, 0xbad
|
||||
WRITE_READ_CSR sie, 0xbad
|
||||
WRITE_READ_CSR stvec, 0xbad
|
||||
WRITE_READ_CSR scounteren, 0xbad
|
||||
|
||||
# Supervisor Configuration
|
||||
# write_read_csr senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||
# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||
|
||||
# Supervisor Trap Handling
|
||||
write_read_csr sscratch, 0xbad
|
||||
write_read_csr sepc, 0xbad
|
||||
write_read_csr scause, 0xbad
|
||||
write_read_csr stval, 0xbad
|
||||
write_read_csr sip, 0xbad
|
||||
WRITE_READ_CSR sscratch, 0xbad
|
||||
WRITE_READ_CSR sepc, 0xbad
|
||||
WRITE_READ_CSR scause, 0xbad
|
||||
WRITE_READ_CSR stval, 0xbad
|
||||
WRITE_READ_CSR sip, 0xbad
|
||||
|
||||
# Supervisor Protection and Translation
|
||||
write_read_csr satp, 0xbad
|
||||
WRITE_READ_CSR satp, 0xbad
|
||||
|
||||
# Machine information Registers
|
||||
write_read_csr mvendorid, 0xbad
|
||||
write_read_csr marchid, 0xbad
|
||||
write_read_csr mimpid, 0xbad
|
||||
write_read_csr mhartid, 0xbad
|
||||
# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||
WRITE_READ_CSR mvendorid, 0xbad
|
||||
WRITE_READ_CSR marchid, 0xbad
|
||||
WRITE_READ_CSR mimpid, 0xbad
|
||||
WRITE_READ_CSR mhartid, 0xbad
|
||||
# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||
|
||||
# Machine Trap Setup
|
||||
write_read_csr mstatus, 0xbad
|
||||
write_read_csr misa, 0xbad
|
||||
write_read_csr medeleg, 0xbad
|
||||
write_read_csr mideleg, 0xbad
|
||||
write_read_csr mie, 0xbad
|
||||
write_read_csr mtvec, 0xbad
|
||||
write_read_csr mcounteren, 0xbad
|
||||
WRITE_READ_CSR mstatus, 0xbad
|
||||
WRITE_READ_CSR misa, 0xbad
|
||||
WRITE_READ_CSR medeleg, 0xbad
|
||||
WRITE_READ_CSR mideleg, 0xbad
|
||||
WRITE_READ_CSR mie, 0xbad
|
||||
WRITE_READ_CSR mtvec, 0xbad
|
||||
WRITE_READ_CSR mcounteren, 0xbad
|
||||
|
||||
# Machine Trap Handling
|
||||
write_read_csr mscratch, 0xbad
|
||||
write_read_csr mepc, 0xbad
|
||||
write_read_csr mcause, 0xbad
|
||||
write_read_csr mtval, 0xbad
|
||||
write_read_csr mip, 0xbad
|
||||
# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||
# write_read_csr mtval2, 0xbad
|
||||
WRITE_READ_CSR mscratch, 0xbad
|
||||
WRITE_READ_CSR mepc, 0xbad
|
||||
WRITE_READ_CSR mcause, 0xbad
|
||||
WRITE_READ_CSR mtval, 0xbad
|
||||
WRITE_READ_CSR mip, 0xbad
|
||||
# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||
# WRITE_READ_CSR mtval2, 0xbad
|
||||
|
||||
# Machine Configuration
|
||||
# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||
# write_read_csr mseccgf, 0xbad
|
||||
# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||
# WRITE_READ_CSR mseccgf, 0xbad
|
||||
|
||||
# Machine Memory Protection
|
||||
write_read_csr pmpcfg0, 0xbad
|
||||
write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||
WRITE_READ_CSR pmpcfg0, 0xbad
|
||||
WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||
|
||||
write_read_csr pmpaddr0, 0xbad
|
||||
write_read_csr pmpaddr1, 0xbad
|
||||
write_read_csr pmpaddr2, 0xbad
|
||||
write_read_csr pmpaddr3, 0xbad
|
||||
write_read_csr pmpaddr4, 0xbad
|
||||
write_read_csr pmpaddr5, 0xbad
|
||||
write_read_csr pmpaddr6, 0xbad
|
||||
write_read_csr pmpaddr7, 0xbad
|
||||
write_read_csr pmpaddr8, 0xbad
|
||||
write_read_csr pmpaddr9, 0xbad
|
||||
write_read_csr pmpaddr10, 0xbad
|
||||
write_read_csr pmpaddr11, 0xbad
|
||||
write_read_csr pmpaddr12, 0xbad
|
||||
write_read_csr pmpaddr13, 0xbad
|
||||
write_read_csr pmpaddr14, 0xbad
|
||||
write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
|
||||
WRITE_READ_CSR pmpaddr0, 0xbad
|
||||
WRITE_READ_CSR pmpaddr1, 0xbad
|
||||
WRITE_READ_CSR pmpaddr2, 0xbad
|
||||
WRITE_READ_CSR pmpaddr3, 0xbad
|
||||
WRITE_READ_CSR pmpaddr4, 0xbad
|
||||
WRITE_READ_CSR pmpaddr5, 0xbad
|
||||
WRITE_READ_CSR pmpaddr6, 0xbad
|
||||
WRITE_READ_CSR pmpaddr7, 0xbad
|
||||
WRITE_READ_CSR pmpaddr8, 0xbad
|
||||
WRITE_READ_CSR pmpaddr9, 0xbad
|
||||
WRITE_READ_CSR pmpaddr10, 0xbad
|
||||
WRITE_READ_CSR pmpaddr11, 0xbad
|
||||
WRITE_READ_CSR pmpaddr12, 0xbad
|
||||
WRITE_READ_CSR pmpaddr13, 0xbad
|
||||
WRITE_READ_CSR pmpaddr14, 0xbad
|
||||
WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
|
||||
|
||||
# Machine Counter/Timers
|
||||
write_read_csr mcycle, 0xbad
|
||||
write_read_csr minstret, 0xbad
|
||||
write_read_csr mhpmcounter3, 0xbad
|
||||
write_read_csr mhpmcounter4, 0xbad
|
||||
write_read_csr mhpmcounter5, 0xbad
|
||||
write_read_csr mhpmcounter6, 0xbad
|
||||
write_read_csr mhpmcounter7, 0xbad
|
||||
write_read_csr mhpmcounter8, 0xbad
|
||||
write_read_csr mhpmcounter9, 0xbad
|
||||
write_read_csr mhpmcounter10, 0xbad
|
||||
write_read_csr mhpmcounter11, 0xbad
|
||||
write_read_csr mhpmcounter12, 0xbad
|
||||
write_read_csr mhpmcounter13, 0xbad
|
||||
write_read_csr mhpmcounter14, 0xbad
|
||||
write_read_csr mhpmcounter15, 0xbad
|
||||
write_read_csr mhpmcounter16, 0xbad
|
||||
write_read_csr mhpmcounter17, 0xbad
|
||||
write_read_csr mhpmcounter18, 0xbad
|
||||
write_read_csr mhpmcounter19, 0xbad
|
||||
write_read_csr mhpmcounter20, 0xbad
|
||||
write_read_csr mhpmcounter21, 0xbad
|
||||
write_read_csr mhpmcounter22, 0xbad
|
||||
write_read_csr mhpmcounter23, 0xbad
|
||||
write_read_csr mhpmcounter24, 0xbad
|
||||
write_read_csr mhpmcounter25, 0xbad
|
||||
write_read_csr mhpmcounter26, 0xbad
|
||||
write_read_csr mhpmcounter27, 0xbad
|
||||
write_read_csr mhpmcounter28, 0xbad
|
||||
write_read_csr mhpmcounter29, 0xbad
|
||||
write_read_csr mhpmcounter30, 0xbad
|
||||
write_read_csr mhpmcounter31, 0xbad
|
||||
WRITE_READ_CSR mcycle, 0xbad
|
||||
WRITE_READ_CSR minstret, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter3, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter4, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter5, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter6, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter7, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter8, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter9, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter10, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter11, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter12, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter13, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter14, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter15, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter16, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter17, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter18, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter19, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter20, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter21, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter22, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter23, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter24, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter25, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter26, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter27, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter28, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter29, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter30, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter31, 0xbad
|
||||
|
||||
# Machine Counter Setup
|
||||
write_read_csr mcountinhibit, 0xbad
|
||||
write_read_csr mhpmevent3, 0xbad
|
||||
write_read_csr mhpmevent4, 0xbad
|
||||
write_read_csr mhpmevent5, 0xbad
|
||||
write_read_csr mhpmevent6, 0xbad
|
||||
write_read_csr mhpmevent7, 0xbad
|
||||
write_read_csr mhpmevent8, 0xbad
|
||||
write_read_csr mhpmevent9, 0xbad
|
||||
write_read_csr mhpmevent10, 0xbad
|
||||
write_read_csr mhpmevent11, 0xbad
|
||||
write_read_csr mhpmevent12, 0xbad
|
||||
write_read_csr mhpmevent13, 0xbad
|
||||
write_read_csr mhpmevent14, 0xbad
|
||||
write_read_csr mhpmevent15, 0xbad
|
||||
write_read_csr mhpmevent16, 0xbad
|
||||
write_read_csr mhpmevent17, 0xbad
|
||||
write_read_csr mhpmevent18, 0xbad
|
||||
write_read_csr mhpmevent19, 0xbad
|
||||
write_read_csr mhpmevent20, 0xbad
|
||||
write_read_csr mhpmevent21, 0xbad
|
||||
write_read_csr mhpmevent22, 0xbad
|
||||
write_read_csr mhpmevent23, 0xbad
|
||||
write_read_csr mhpmevent24, 0xbad
|
||||
write_read_csr mhpmevent25, 0xbad
|
||||
write_read_csr mhpmevent26, 0xbad
|
||||
write_read_csr mhpmevent27, 0xbad
|
||||
write_read_csr mhpmevent28, 0xbad
|
||||
write_read_csr mhpmevent29, 0xbad
|
||||
write_read_csr mhpmevent30, 0xbad
|
||||
write_read_csr mhpmevent31, 0xbad
|
||||
WRITE_READ_CSR mcountinhibit, 0xbad
|
||||
WRITE_READ_CSR mhpmevent3, 0xbad
|
||||
WRITE_READ_CSR mhpmevent4, 0xbad
|
||||
WRITE_READ_CSR mhpmevent5, 0xbad
|
||||
WRITE_READ_CSR mhpmevent6, 0xbad
|
||||
WRITE_READ_CSR mhpmevent7, 0xbad
|
||||
WRITE_READ_CSR mhpmevent8, 0xbad
|
||||
WRITE_READ_CSR mhpmevent9, 0xbad
|
||||
WRITE_READ_CSR mhpmevent10, 0xbad
|
||||
WRITE_READ_CSR mhpmevent11, 0xbad
|
||||
WRITE_READ_CSR mhpmevent12, 0xbad
|
||||
WRITE_READ_CSR mhpmevent13, 0xbad
|
||||
WRITE_READ_CSR mhpmevent14, 0xbad
|
||||
WRITE_READ_CSR mhpmevent15, 0xbad
|
||||
WRITE_READ_CSR mhpmevent16, 0xbad
|
||||
WRITE_READ_CSR mhpmevent17, 0xbad
|
||||
WRITE_READ_CSR mhpmevent18, 0xbad
|
||||
WRITE_READ_CSR mhpmevent19, 0xbad
|
||||
WRITE_READ_CSR mhpmevent20, 0xbad
|
||||
WRITE_READ_CSR mhpmevent21, 0xbad
|
||||
WRITE_READ_CSR mhpmevent22, 0xbad
|
||||
WRITE_READ_CSR mhpmevent23, 0xbad
|
||||
WRITE_READ_CSR mhpmevent24, 0xbad
|
||||
WRITE_READ_CSR mhpmevent25, 0xbad
|
||||
WRITE_READ_CSR mhpmevent26, 0xbad
|
||||
WRITE_READ_CSR mhpmevent27, 0xbad
|
||||
WRITE_READ_CSR mhpmevent28, 0xbad
|
||||
WRITE_READ_CSR mhpmevent29, 0xbad
|
||||
WRITE_READ_CSR mhpmevent30, 0xbad
|
||||
WRITE_READ_CSR mhpmevent31, 0xbad
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -22,8 +22,18 @@
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions
|
||||
// Ideally this should mean that a test can be written by simply adding .8byte statements as below.
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
j test_loop_setup // begin test loop/table tests instead of executing inline code.
|
||||
|
||||
INIT_TEST_TABLE
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
|
||||
.align 3
|
||||
test_cases:
|
||||
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
# Test Contents
|
||||
|
||||
@ -22,8 +22,19 @@
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions
|
||||
// Ideally this should mean that a test can be written by simply adding .8byte statements as below.
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
j test_loop_setup // begin test loop/table tests instead of executing inline code.
|
||||
|
||||
INIT_TEST_TABLE
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
|
||||
# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook
|
||||
.align 3
|
||||
test_cases:
|
||||
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
# Test Contents
|
||||
@ -39,7 +50,6 @@
|
||||
#
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
|
||||
# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook
|
||||
|
||||
# =========== test 12.3.1.1 Page Table Translation ===========
|
||||
|
||||
|
||||
@ -35,8 +35,19 @@
|
||||
#define PLIC_RANGE 0x03FFFFFF
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions
|
||||
// Ideally this should mean that a test can be written by simply adding .8byte statements as below.
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
j test_loop_setup // begin test loop/table tests instead of executing inline code.
|
||||
|
||||
INIT_TEST_TABLE
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
|
||||
# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook
|
||||
.align 3
|
||||
test_cases:
|
||||
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
# Test Contents
|
||||
|
||||
@ -22,8 +22,19 @@
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions
|
||||
// Ideally this should mean that a test can be written by simply adding .8byte statements as below.
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
j test_loop_setup // begin test loop/table tests instead of executing inline code.
|
||||
|
||||
INIT_TEST_TABLE
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
|
||||
# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook
|
||||
.align 3
|
||||
test_cases:
|
||||
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
# Test Contents
|
||||
|
||||
@ -23,6 +23,9 @@
|
||||
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
|
||||
.macro INIT_TESTS
|
||||
|
||||
RVTEST_ISA("RV64I")
|
||||
|
||||
.section .text.init
|
||||
@ -56,9 +59,9 @@ RVTEST_CODE_BEGIN
|
||||
li a1, 0
|
||||
li a2, 0 // reset trap handler inputs to zero
|
||||
|
||||
// go to first test!
|
||||
j test_setup
|
||||
|
||||
// go to beginning of S file where we can decide between using the test data loop
|
||||
// or using the macro inline code insertion
|
||||
j s_file_begin
|
||||
|
||||
// ---------------------------------------------------------------------------------------------
|
||||
// General traps Handler
|
||||
@ -230,6 +233,9 @@ instrfault:
|
||||
ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page)
|
||||
j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
|
||||
|
||||
illegalinstr:
|
||||
j trapreturn // return to the code after recording the mcause
|
||||
|
||||
accessfault:
|
||||
// *** What do I have to do here?
|
||||
j trapreturn
|
||||
@ -243,7 +249,7 @@ accessfault:
|
||||
trap_handler_vector_table:
|
||||
.8byte segfault // 0: instruction address misaligned
|
||||
.8byte instrfault // 1: instruction access fault
|
||||
.8byte segfault // 2: illegal instruction
|
||||
.8byte illegalinstr // 2: illegal instruction
|
||||
.8byte segfault // 3: breakpoint
|
||||
.8byte segfault // 4: load address misaligned
|
||||
.8byte accessfault // 5: load access fault
|
||||
@ -265,6 +271,249 @@ trap_return_pagetype_table:
|
||||
.8byte 0x1E // 2: gigapage has 30 offset bits
|
||||
.8byte 0x27 // 3: terapage has 39 offset bits
|
||||
|
||||
.endm
|
||||
|
||||
// Test Summary table!
|
||||
|
||||
// Test Name : Description : Fault output value : Normal output values
|
||||
// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------
|
||||
// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None
|
||||
// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None
|
||||
// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None
|
||||
// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None
|
||||
// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111)
|
||||
// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_baremetal : satp.MODE = bare metal : None : None
|
||||
// goto_sv39 : satp.MODE = sv39 : None : None
|
||||
// goto_sv48 : satp.MODE = sv48 : None : None
|
||||
// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR
|
||||
// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11
|
||||
|
||||
// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value
|
||||
|
||||
.macro WRITE64 ADDR VAL
|
||||
// attempt to write VAL to ADDR
|
||||
// Success outputs:
|
||||
// None
|
||||
// Fault outputs:
|
||||
// 0x6: misaligned address
|
||||
// 0x7: access fault
|
||||
// 0xf: page fault
|
||||
li x29, \VAL
|
||||
li x30, \ADDR
|
||||
sd x29, 0(x30)
|
||||
.endm
|
||||
|
||||
.macro WRITE32 ADDR VAL
|
||||
// all write tests have the same description/outputs as write64
|
||||
li x29, \VAL
|
||||
li x30, \ADDR
|
||||
sw x29, 0(x30)
|
||||
.endm
|
||||
|
||||
.macro WRITE16 ADDR VAL
|
||||
// all write tests have the same description/outputs as write64
|
||||
li x29, \VAL
|
||||
li x30, \ADDR
|
||||
sh x29, 0(x30)
|
||||
.endm
|
||||
|
||||
.macro WRITE08 ADDR VAL
|
||||
// all write tests have the same description/outputs as write64
|
||||
li x29, \VAL
|
||||
li x30, \ADDR
|
||||
sb x29, 0(x30)
|
||||
.endm
|
||||
|
||||
.macro READ64 ADDR
|
||||
// Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value
|
||||
// Success outputs:
|
||||
// value read out from ADDR
|
||||
// Fault outputs:
|
||||
// One of the following followed by 0xBAD
|
||||
// 0x4: misaligned address
|
||||
// 0x5: access fault
|
||||
// 0xD: page fault
|
||||
li x7, 0xBAD // bad value that will be overwritten on good reads.
|
||||
li x29, \ADDR
|
||||
ld x7, 0(x29)
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro READ32 ADDR
|
||||
// All reads have the same description/outputs as read64.
|
||||
// They will store the sign extended value of what was read out at ADDR
|
||||
li x7, 0xBAD // bad value that will be overwritten on good reads.
|
||||
li x29, \ADDR
|
||||
lw x7, 0(x29)
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro READ16 ADDR
|
||||
// All reads have the same description/outputs as read64.
|
||||
// They will store the sign extended value of what was read out at ADDR
|
||||
li x7, 0xBAD // bad value that will be overwritten on good reads.
|
||||
li x29, \ADDR
|
||||
lh x7, 0(x29)
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro READ08 ADDR
|
||||
// All reads have the same description/outputs as read64.
|
||||
// They will store the sign extended value of what was read out at ADDR
|
||||
li x7, 0xBAD // bad value that will be overwritten on good reads.
|
||||
li x29, \ADDR
|
||||
lb x7, 0(x29)
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
// These goto_x_mode tests all involve invoking the trap handler,
|
||||
// So their outputs are inevitably:
|
||||
// 0x8: test called from U mode
|
||||
// 0x9: test called from S mode
|
||||
// 0xB: test called from M mode
|
||||
// they generally do not fault or cause issues as long as these modes are enabled
|
||||
// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
|
||||
|
||||
.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE
|
||||
li a0, 2 // determine trap handler behavior (go to machine mode)
|
||||
li a1, \RETURN_VPN // return VPN
|
||||
li a2, \RETURN_PAGETYPE // return page types
|
||||
ecall // writes mcause to the output.
|
||||
// now in S mode
|
||||
.endm
|
||||
|
||||
.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE
|
||||
li a0, 3 // determine trap handler behavior (go to supervisor mode)
|
||||
li a1, \RETURN_VPN // return VPN
|
||||
li a2, \RETURN_PAGETYPE // return page types
|
||||
ecall // writes mcause to the output.
|
||||
// now in S mode
|
||||
.endm
|
||||
|
||||
.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE
|
||||
li a0, 4 // determine trap handler behavior (go to user mode)
|
||||
li a1, \RETURN_VPN // return VPN
|
||||
li a2, \RETURN_PAGETYPE // return page types
|
||||
ecall // writes mcause to the output.
|
||||
// now in S mode
|
||||
.endm
|
||||
|
||||
// These tests change virtual memory settings, turning it on/off and changing between types.
|
||||
// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy?
|
||||
|
||||
.macro GOTO_BAREMETAL
|
||||
// Turn translation off
|
||||
li x7, 0 // satp.MODE value for bare metal (0)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro GOTO_SV39
|
||||
// Turn on sv39 virtual memory
|
||||
li x7, 8 // satp.MODE value for Sv39 (8)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro GOTO_SV48
|
||||
// Turn on sv48 virtual memory
|
||||
li x7, 9 // satp.MODE value for Sv39 (8)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro WRITE_READ_CSR CSR VAL
|
||||
// attempt to write CSR with VAL. Note: this also tests read access to CSR
|
||||
// Success outputs:
|
||||
// value read back out from CSR after writing
|
||||
// Fault outputs:
|
||||
// The previous CSR value before write attempt
|
||||
// *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
|
||||
li x30, 0xbad // load bad value to be overwritten by csrr
|
||||
li x29, \VAL
|
||||
csrw \CSR\(), x29
|
||||
csrr x30, \CSR
|
||||
sd x30, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro CSR_R_ACCESS CSR
|
||||
// verify that a csr is accessible to read but not to write
|
||||
// Success outputs:
|
||||
// 0x2, then
|
||||
// 0x11 *** consider changing to something more meaningful
|
||||
// Fault outputs:
|
||||
// 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault?
|
||||
csrr x29, \CSR
|
||||
csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR
|
||||
csrr x30, \CSR
|
||||
bne x30, x29, 1f // 1f represents write_access
|
||||
li x30, 0x11 // Write failed, confirming read only permissions.
|
||||
j 2f // j r_access_end
|
||||
1: // w_access (write succeeded, violating read-only)
|
||||
li x30, 0xBAD
|
||||
2: // r_access end
|
||||
sd x30, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro EXECUTE_AT_ADDRESS ADDR
|
||||
// Execute the code already written to ADDR, returning the value in x7.
|
||||
// *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR
|
||||
// Assumes the code modifies x7, usually to become 0x111.
|
||||
// Sample code: 0x11100393 (li x7, 0x111), 0x00008067 (ret)
|
||||
// Success outputs:
|
||||
// modified value of x7. (0x111 if you use the sample code)
|
||||
// Fault outputs:
|
||||
// One of the following followed by 0xBAD
|
||||
// 0x0: misaligned address
|
||||
// 0x1: access fault
|
||||
// 0xC: page fault
|
||||
fence.i // forces caches and main memory to sync so execution code written to ADDR can run.
|
||||
li x7, 0xBAD
|
||||
li x28, \ADDR
|
||||
jalr x28 // jump to executable test code
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro END_TESTS
|
||||
// invokes one final ecall to return to machine mode then terminates this program, so the output is
|
||||
// 0x8: termination called from U mode
|
||||
// 0x9: termination called from S mode
|
||||
// 0xB: termination called from M mode
|
||||
j terminate_test
|
||||
|
||||
.endm
|
||||
|
||||
// ---------------------------------------------------------------------------------------------
|
||||
// Test Handler
|
||||
//
|
||||
@ -274,17 +523,18 @@ trap_return_pagetype_table:
|
||||
// Input parameters:
|
||||
//
|
||||
// x28:
|
||||
// Address input for the test taking place (think address to read/write, new address to return to, etc...)
|
||||
// Address input for the test taking place (think: address to read/write, new address to return to, etc...)
|
||||
//
|
||||
// x29:
|
||||
// Value input for the test taking place (think value to write, any other extra info needed)
|
||||
// Value input for the test taking place (think: value to write, any other extra info needed)
|
||||
//
|
||||
// x30:
|
||||
// Test type input that determines which kind of test will take place. Encoding for this input is in the table/case statements below
|
||||
//
|
||||
// Label for the location of the test that's about to take place
|
||||
// ------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
test_setup:
|
||||
.macro INIT_TEST_TABLE // *** Consider renaming this test. to what???
|
||||
|
||||
test_loop_setup:
|
||||
la x5, test_cases
|
||||
|
||||
test_loop:
|
||||
@ -407,30 +657,15 @@ goto_u_mode:
|
||||
|
||||
goto_baremetal:
|
||||
// Turn translation off
|
||||
li x7, 0 // satp.MODE value for bare metal (0)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field.
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
GOTO_BAREMETAL
|
||||
j test_loop // go to next test case
|
||||
|
||||
goto_sv39:
|
||||
li x7, 8 // satp.MODE value for Sv39 (8)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field.
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
GOTO_SV39
|
||||
j test_loop // go to next test case
|
||||
|
||||
goto_sv48:
|
||||
li x7, 9 // satp.MODE value for Sv48
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field.
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
GOTO_SV48
|
||||
j test_loop // go to next test case
|
||||
|
||||
write_mxr_sum:
|
||||
@ -448,14 +683,16 @@ write_pmpcfg_0:
|
||||
// writes the value in x29 to the pmpcfg register specified in x28.
|
||||
// then writes the final value of pmpcfgX to the output.
|
||||
li x7, 0x0
|
||||
bne x7, x28, write_pmpcfg_2
|
||||
csrw pmpcfg0, x29
|
||||
csrr x30, pmpcfg0
|
||||
j write_pmpcfg_end
|
||||
|
||||
write_pmpcfg_2:
|
||||
li x7, 0x2
|
||||
bne x7, x28, write_pmpcfg_end
|
||||
csrw pmpcfg2, x29
|
||||
csrr x30, pmpcfg2 // I would use csrrw but we need the value AFTER the csr has been written
|
||||
j write_pmpcfg_end
|
||||
|
||||
write_pmpcfg_end:
|
||||
sd x30, 0(x6)
|
||||
addi x6, x6, 8
|
||||
@ -463,103 +700,104 @@ write_pmpcfg_end:
|
||||
j test_loop
|
||||
|
||||
write_pmpaddr_0:
|
||||
// write_read_csr pmpaddr0, x29
|
||||
// writes the value in x29 to the pmpaddr register specified in x28.
|
||||
// then writes the final value of pmpaddrX to the output.
|
||||
li x7, 0x0
|
||||
bne x7, x28, write_pmpaddr_1
|
||||
csrw pmpaddr0, x29
|
||||
csrr x30, pmpaddr0
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_1:
|
||||
li x7, 0x1
|
||||
bne x7, x28, write_pmpaddr_2
|
||||
csrw pmpaddr1, x29
|
||||
csrr x30, pmpaddr1
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_2:
|
||||
li x7, 0x2
|
||||
bne x7, x28, write_pmpaddr_3
|
||||
csrw pmpaddr2, x29
|
||||
csrr x30, pmpaddr2
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_3:
|
||||
li x7, 0x3
|
||||
bne x7, x28, write_pmpaddr_4
|
||||
csrw pmpaddr3, x29
|
||||
csrr x30, pmpaddr3
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_4:
|
||||
li x7, 0x4
|
||||
bne x7, x28, write_pmpaddr_5
|
||||
csrw pmpaddr4, x29
|
||||
csrr x30, pmpaddr4
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_5:
|
||||
li x7, 0x5
|
||||
bne x7, x28, write_pmpaddr_6
|
||||
csrw pmpaddr5, x29
|
||||
csrr x30, pmpaddr5
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_6:
|
||||
li x7, 0x6
|
||||
bne x7, x28, write_pmpaddr_7
|
||||
csrw pmpaddr6, x29
|
||||
csrr x30, pmpaddr6
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_7:
|
||||
li x7, 0x7
|
||||
bne x7, x28, write_pmpaddr_8
|
||||
csrw pmpaddr7, x29
|
||||
csrr x30, pmpaddr7
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_8:
|
||||
li x7, 0x8
|
||||
bne x7, x28, write_pmpaddr_9
|
||||
csrw pmpaddr8, x29
|
||||
csrr x30, pmpaddr8
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_9:
|
||||
li x7, 0x9
|
||||
bne x7, x28, write_pmpaddr_10
|
||||
csrw pmpaddr9, x29
|
||||
csrr x30, pmpaddr9
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_10:
|
||||
li x7, 0xA
|
||||
bne x7, x28, write_pmpaddr_11
|
||||
csrw pmpaddr10, x29
|
||||
csrr x30, pmpaddr10
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_11:
|
||||
li x7, 0xB
|
||||
bne x7, x28, write_pmpaddr_12
|
||||
csrw pmpaddr11, x29
|
||||
csrr x30, pmpaddr11
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_12:
|
||||
li x7, 0xC
|
||||
bne x7, x28, write_pmpaddr_13
|
||||
csrw pmpaddr12, x29
|
||||
csrr x30, pmpaddr12
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_13:
|
||||
li x7, 0xD
|
||||
bne x7, x28, write_pmpaddr_14
|
||||
csrw pmpaddr13, x29
|
||||
csrr x30, pmpaddr13
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_14:
|
||||
li x7, 0xE
|
||||
bne x7, x28, write_pmpaddr_15
|
||||
csrw pmpaddr14, x29
|
||||
csrr x30, pmpaddr14
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_15:
|
||||
li x7, 0xF
|
||||
bne x7, x28, write_pmpaddr_end
|
||||
csrw pmpaddr15, x29
|
||||
csrr x30, pmpaddr15
|
||||
j write_pmpaddr_end
|
||||
|
||||
write_pmpaddr_end:
|
||||
sd x30, 0(x6)
|
||||
addi x6, x6, 8
|
||||
@ -577,6 +815,10 @@ executable_test:
|
||||
addi x16, x16, 8
|
||||
j test_loop
|
||||
|
||||
.endm
|
||||
|
||||
// notably, terminate_test is not a part of the test table macro because it needs to be defined
|
||||
// in any type of test, macro or test table, for the trap handler to work
|
||||
terminate_test:
|
||||
|
||||
li a0, 2 // Trap handler behavior (go to machine mode)
|
||||
@ -586,6 +828,8 @@ terminate_test:
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
.macro TEST_STACK_AND_DATA
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
@ -619,6 +863,4 @@ gpr_save:
|
||||
|
||||
#endif
|
||||
|
||||
.align 3
|
||||
test_cases:
|
||||
|
||||
.endm
|
||||
|
||||
@ -21,17 +21,19 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-MACROS-64.h"
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
|
||||
// Test 5.2.3.1: testing Read-only access to Machine info CSRs
|
||||
CSR_R_ACCESS mvendorid
|
||||
CSR_R_ACCESS marchid
|
||||
CSR_R_ACCESS mimpid
|
||||
CSR_R_ACCESS mhartid
|
||||
# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22
|
||||
|
||||
csr_r_access mvendorid
|
||||
csr_r_access marchid
|
||||
csr_r_access mimpid
|
||||
csr_r_access mhartid
|
||||
# csr_r_access mconfigptr # Unimplemented in spike as of 31 Jan 22
|
||||
END_TESTS
|
||||
|
||||
|
||||
END_TESTS
|
||||
TEST_STACK_AND_DATA
|
||||
Loading…
Reference in New Issue
Block a user