David Harris
|
5d5274ec73
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-07 06:32:29 -04:00 |
|
David Harris
|
2bab3f769b
|
Renamed tlb ReadLines to Matches
|
2021-07-07 06:32:26 -04:00 |
|
Abe
|
b757c96b2d
|
Changed SvMode to SVMode on line 76
|
2021-07-06 23:28:58 -04:00 |
|
David Harris
|
af619dcd75
|
Added ASID matching for CAM
|
2021-07-06 18:56:25 -04:00 |
|
Kip Macsai-Goren
|
8350622f65
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-06 18:54:41 -04:00 |
|
David Harris
|
7d857cf4bd
|
more TLB name touchups
|
2021-07-06 18:39:30 -04:00 |
|
Kip Macsai-Goren
|
e08a578908
|
fixed upper bits page fault signal
|
2021-07-06 18:32:47 -04:00 |
|
David Harris
|
2e2aa2a972
|
connected signals in tlb by name instead of .*
|
2021-07-06 17:22:10 -04:00 |
|
David Harris
|
ee3a321002
|
changed tlbphysicalpagemask to structural
|
2021-07-06 17:16:58 -04:00 |
|
David Harris
|
f960561cbb
|
changed tlbphysicalpagemask to structural
|
2021-07-06 17:08:04 -04:00 |
|
David Harris
|
032c38b7e7
|
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
|
2021-07-06 15:29:42 -04:00 |
|
Ross Thompson
|
3345ed7ff4
|
Merged several of the load/store/instruction access faults inside the mmu.
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
|
2021-07-06 13:43:53 -05:00 |
|
David Harris
|
30fdd7abc8
|
Cleaned up tlb output muxing
|
2021-07-06 10:44:05 -04:00 |
|
David Harris
|
d58cad89a8
|
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
|
2021-07-06 10:38:30 -04:00 |
|
David Harris
|
694badcc6b
|
Created tlbcontrol module to hide details
|
2021-07-06 03:25:11 -04:00 |
|
David Harris
|
8b23162d6d
|
Fixed adrdecs to use Access signals for TIMs
|
2021-07-05 23:42:58 -04:00 |
|
David Harris
|
71711c54c9
|
Don't generate HPTW when MEM_VIRTMEM=0
|
2021-07-05 23:35:44 -04:00 |
|
David Harris
|
179c8d3ed4
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-05 23:23:17 -04:00 |
|
David Harris
|
6bac566bb7
|
Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
|
2021-07-05 20:35:31 -04:00 |
|
Ross Thompson
|
530ddd667b
|
Fixed combo loop in the page table walker.
|
2021-07-05 16:37:26 -05:00 |
|
Ross Thompson
|
2a62ee2e70
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-05 16:07:27 -05:00 |
|
David Harris
|
b23192cf1b
|
Gave names to for loops in generate blocks for ease of reference
|
2021-07-04 18:52:16 -04:00 |
|
David Harris
|
07f2064c19
|
Touched up TLB D and A bit checks
|
2021-07-04 18:17:09 -04:00 |
|
Ross Thompson
|
b2c5c3f637
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-04 17:07:57 -05:00 |
|
David Harris
|
b0f199b574
|
Fixed TLB_ENTRIES merge conflict and handling of global PTEs
|
2021-07-04 18:05:22 -04:00 |
|
Ross Thompson
|
02721c29dc
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-04 16:54:31 -05:00 |
|
David Harris
|
8b707f7703
|
Added ASID & Global PTE handling to TLB CAM
|
2021-07-04 17:53:08 -04:00 |
|
David Harris
|
80666f0a71
|
Added ASID & Global PTE handling to TLB CAM
|
2021-07-04 17:52:00 -04:00 |
|
Ross Thompson
|
a252416535
|
Removed the TranslationVAdrQ as it is not necessary.
|
2021-07-04 16:49:34 -05:00 |
|
Ross Thompson
|
7f62808544
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-04 16:19:39 -05:00 |
|
David Harris
|
07ef67e537
|
Restructured TLB Read as AND-OR operation with one-hot match/read line
|
2021-07-04 17:01:22 -04:00 |
|
David Harris
|
8337d6df68
|
Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders
|
2021-07-04 16:33:13 -04:00 |
|
David Harris
|
c281539f36
|
TLB cleanup
|
2021-07-04 14:59:04 -04:00 |
|
David Harris
|
81742ef9e2
|
TLB cleanup
|
2021-07-04 14:37:53 -04:00 |
|
David Harris
|
152923e552
|
TLB minor organization
|
2021-07-04 14:30:56 -04:00 |
|
David Harris
|
7e22ae973e
|
Fixed MPRV and MXR checks in TLB
|
2021-07-04 13:20:29 -04:00 |
|
David Harris
|
1b39481a16
|
TLB mux and swizzling cleanup
|
2021-07-04 12:53:52 -04:00 |
|
David Harris
|
735f3b4217
|
Replaced generates with arrays in TLB
|
2021-07-04 12:32:27 -04:00 |
|
David Harris
|
67e191c6f3
|
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
|
2021-07-04 11:39:59 -04:00 |
|
David Harris
|
ccd9c05303
|
Switched to array notation for pmpchecker
|
2021-07-04 10:51:56 -04:00 |
|
David Harris
|
9645b023c9
|
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
|
2021-07-04 01:19:38 -04:00 |
|
Ross Thompson
|
9f16d08d0d
|
removed mmustall and finished port annotations on ptw and lsuArb.
|
2021-07-03 16:06:09 -05:00 |
|
David Harris
|
1fa4abf7b6
|
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
|
2021-07-03 03:29:33 -04:00 |
|
David Harris
|
d44916dacf
|
Cleaned up PMA/PMP checker unused code
|
2021-07-03 02:25:31 -04:00 |
|
Ross Thompson
|
cf688bd3f6
|
Fixed up the physical address generation for 64 bit page table walker.
|
2021-07-02 15:49:32 -05:00 |
|
Ross Thompson
|
8e3149517a
|
Fixed up the bit widths on the page table walker for rv32.
|
2021-07-02 15:45:05 -05:00 |
|
Ross Thompson
|
7b3716c281
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-02 13:56:49 -05:00 |
|
David Harris
|
c85e0df1ff
|
Optimized PMP checker logic and added support for configurable number of PMP registers
|
2021-07-02 11:04:13 -04:00 |
|
Ross Thompson
|
118dfa9cec
|
added page table walker fault exit for icache.
|
2021-07-01 17:59:55 -05:00 |
|
Ross Thompson
|
61027f650c
|
OMG. It's working!
|
2021-07-01 17:37:53 -05:00 |
|