bbracker
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d3059dd04c
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fix UART RX FIFO bug where tail pointer can overtake head pointer
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2021-07-22 02:09:41 -04:00 |
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bbracker
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f9b6bd91f5
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fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk
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2021-07-20 17:55:44 -04:00 |
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David Harris
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1f3dfa20f6
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flag for optional boottim
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2021-07-20 14:46:37 -04:00 |
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bbracker
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bc5222e721
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put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests
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2021-07-19 16:19:24 -04:00 |
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bbracker
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64e0fe4c5a
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whoops MTIMECMP is always 64 bits
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2021-07-19 15:40:53 -04:00 |
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bbracker
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cd469035be
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make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
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2021-07-19 15:13:03 -04:00 |
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David Harris
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004cac91e1
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Simplified PLIC with generate
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2021-07-04 19:17:15 -04:00 |
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David Harris
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0aae58abed
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Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb
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2021-07-04 19:02:56 -04:00 |
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David Harris
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b23192cf1b
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Gave names to for loops in generate blocks for ease of reference
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2021-07-04 18:52:16 -04:00 |
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bbracker
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9c84ab436a
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for GPIO give priority to clearing interrupts
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2021-07-04 17:20:16 -04:00 |
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David Harris
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67e191c6f3
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Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
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2021-07-04 11:39:59 -04:00 |
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David Harris
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accbebfa6f
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Commented out some unused modules
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2021-07-04 01:40:27 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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David Harris
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1fa4abf7b6
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Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
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2021-07-03 03:29:33 -04:00 |
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Kip Macsai-Goren
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d7e518991e
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Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
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2021-06-24 20:01:11 -04:00 |
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David Harris
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fa51ab9f68
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Refactored pmachecker to have adrdecs used in uncore
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2021-06-23 01:41:00 -04:00 |
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bbracker
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303f8e2a7f
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give EBU a dedicated PMA unit as just an address decoder
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2021-06-22 18:28:08 -04:00 |
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David Harris
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d2ec04564b
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Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
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2021-06-20 22:59:04 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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336936cc39
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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5a661a7392
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provide time and timeh CSRs based on CLINT's counter
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2021-06-17 08:38:30 -04:00 |
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bbracker
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7b98e7aa2f
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mcause test fixes and s-mode interrupt bugfix
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2021-06-16 17:37:08 -04:00 |
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Ross Thompson
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294f01cbd8
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fixed the mtime register.
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2021-06-11 13:50:13 -05:00 |
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David Harris
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d386929c0e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-10 10:47:55 -04:00 |
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David Harris
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802238643a
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Removed two cycles of latency from the DTIM
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2021-06-10 10:30:24 -04:00 |
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bbracker
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f272cd46d8
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peripheral lint fixes
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2021-06-10 10:19:10 -04:00 |
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bbracker
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d4aeb1c387
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merge
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2021-06-10 10:03:01 -04:00 |
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bbracker
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79e798a641
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UART improved and added more reg read side effects
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2021-06-10 09:53:48 -04:00 |
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David Harris
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01d6ca1e2a
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Fixed lint WIDTH errors
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2021-06-09 20:58:20 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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bbracker
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e7e4105931
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* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
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2021-06-08 12:32:46 -04:00 |
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bbracker
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4e765ee1c5
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expanded GPIO testing and caught small GPIO bug
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2021-06-03 10:03:09 -04:00 |
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bbracker
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bf6337f2f7
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plic implementation optimizations
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2021-05-19 18:10:48 +00:00 |
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David Harris
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afd6153044
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Rolled back fflush on uart. Use -syncio in Modelsim command line instead.
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2021-05-03 20:04:44 -04:00 |
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David Harris
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d07a7fd0f8
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Flush uart print statements on \n
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2021-05-03 19:51:51 -04:00 |
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David Harris
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93466a0b2a
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Flush uart print statements on \n
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2021-05-03 19:41:37 -04:00 |
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David Harris
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58ce0fbbcc
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Flush uart print statements on \n
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2021-05-03 19:37:45 -04:00 |
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David Harris
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233726e8d8
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Flush uart print statements on \n
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2021-05-03 19:25:28 -04:00 |
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bbracker
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182bfdbb0e
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rv32 plic test and lint fixes
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2021-04-30 06:26:31 -04:00 |
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Ross Thompson
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8e5409af66
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Icache integrated!
Merge branch 'icache-almost-working' into main
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2021-04-26 11:48:58 -05:00 |
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Ross Thompson
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6e803b724e
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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bbracker
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86946266cf
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thomas fixed it before I did
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2021-04-24 09:38:52 -04:00 |
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bbracker
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a3487a9e47
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do script refactor
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2021-04-24 09:32:09 -04:00 |
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Thomas Fleming
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38236e9172
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Implement first pass at the PMA checker
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2021-04-22 15:34:02 -04:00 |
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bbracker
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74b35ac57a
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greatly improved PLIC register interface
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2021-04-22 11:22:01 -04:00 |
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bbracker
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368c94d4ff
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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bbracker
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8f7ddcfdff
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rv64 interrupt servicing
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2021-04-14 10:19:42 -04:00 |
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Ross Thompson
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4322694f7a
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Switch to use RV64IC for the benchmarks.
Still not working correctly with the icache.
instr
addr correct got
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2021-04-07 19:12:43 -05:00 |
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bbracker
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38017e6aae
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declare memread signal
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2021-04-05 08:13:01 -04:00 |
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bbracker
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a4c3afb847
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PLIC claim reg side effects now check for memread signal
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2021-04-05 08:03:14 -04:00 |
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