Ross Thompson
91b51c698e
Minor changes to dcache.
2021-08-17 15:22:10 -05:00
Ross Thompson
6a6d5e9b15
Added documentation about how the dcache and ptw interact.
2021-08-12 18:05:36 -05:00
Ross Thompson
565c01709d
Removed unused states from dcache fsm.
2021-08-11 17:06:09 -05:00
Ross Thompson
4b25fed6d8
Simplified Dcache by sharing the read data mux with the victim selection mux.
2021-08-11 16:55:55 -05:00
Ross Thompson
67c1028862
Dcache and LSU clean up.
2021-08-10 13:36:21 -05:00
Ross Thompson
cce0571925
Fixed another bug with the atomic instrucitons implemention in the dcache.
2021-08-08 22:50:31 -05:00
Ross Thompson
d3be04b7de
Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the
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cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
2021-08-08 11:42:10 -05:00
Ross Thompson
fc7016eea6
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
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Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
Ross Thompson
7b9e53fbe5
Removed 1 cycle delay on store miss.
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Changed some logic to partially support atomics.
2021-07-30 14:00:51 -05:00
Ross Thompson
915d8136e5
Fixed bug which caused stores to take an extra clock cycle.
2021-07-26 12:22:53 -05:00
Ross Thompson
60177b92a6
Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation.
2021-07-25 23:14:28 -05:00
Ross Thompson
3e916da36e
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
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In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
Ross Thompson
551e3491af
Moved the ReadDataW register into the datapath.
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The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
9c90b4bdf7
Fixed bug with the itlb fault not dcache ptw ready state to ready state.
2021-07-22 14:04:56 -05:00
Ross Thompson
b4029a2848
Cleaned up icache and dcache.
2021-07-22 11:06:44 -05:00
Ross Thompson
25a8920a69
Tested all numbers of ways for dcache 1, 2, 4, and 8.
2021-07-22 10:38:07 -05:00
Ross Thompson
313bc5255c
Improved address bus names and usages in the walker, dcache, and tlbs.
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Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Ross Thompson
310b454fa1
Added comment about better muxing.
2021-07-21 14:40:14 -05:00
Ross Thompson
5860f147d4
4 way set associative is now working.
2021-07-21 14:01:14 -05:00
Ross Thompson
e0990535e1
Fixed remaining bugs in 2 way set associative dcache.
2021-07-21 10:35:23 -05:00
Ross Thompson
3f780f012a
Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux.
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Also forgot to include cacheLRU.sv file.
2021-07-20 23:17:42 -05:00
Ross Thompson
14e949d6e3
Partially working 2 way set associative d cache.
2021-07-20 17:51:42 -05:00
Ross Thompson
00081ebc68
Replaced FinalReadDataM with ReadDataM in dcache.
2021-07-20 13:27:29 -05:00
David Harris
e1a1a8395e
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 08:57:13 -04:00
Ross Thompson
365485bd8b
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
Ross Thompson
bf3ca50a9a
Furture simplification of the dcache ReadDataW update.
2021-07-19 12:46:31 -05:00
Ross Thompson
b61dad4b83
Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
2021-07-19 12:32:16 -05:00
Ross Thompson
4d53b9002f
Broken.
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Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
bbracker
67eb1f5c6b
change sram1rw to have a small delay so that we don't have signals changing on clock edges
2021-07-19 11:30:07 -04:00
Ross Thompson
009c5314b4
Fixed LRSC in 64bit version. 32bit version is broken.
2021-07-17 20:58:49 -05:00
Ross Thompson
1aac97030a
Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before.
2021-07-17 18:26:29 -05:00
Ross Thompson
0b3dc288ec
Made furture progress in the mmu tests.
2021-07-16 15:56:06 -05:00
Ross Thompson
6521d2b468
Also changed the shadow ram's dcache copy widths.
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Merge branch 'dcache' into main
2021-07-16 14:21:09 -05:00
Ross Thompson
46bce70e42
Fixed walker fault interaction with dcache.
2021-07-16 12:22:13 -05:00
Ross Thompson
e0f719d513
Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
2021-07-16 11:12:57 -05:00
Kip Macsai-Goren
abd5b1c02d
Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
2021-07-15 18:30:29 -04:00
Ross Thompson
b9902b0560
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
2021-07-15 11:00:42 -05:00
Ross Thompson
8610ef204c
Renamed DCacheStall to LSUStall in hart and hazard.
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Added missing logic in lsu.
2021-07-15 10:16:16 -05:00
Ross Thompson
704f4f724e
dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231
Finally have the ptw correctly walking through the dcache to update the itlb.
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Still not working fully.
2021-07-14 22:26:07 -05:00
Ross Thompson
c79650b508
Added d cache StallW checks for any time the cache wants to go to STATE_READY.
2021-07-14 17:25:50 -05:00
Ross Thompson
2c946a282f
Fixed d cache not honoring StallW for uncache writes and reads.
2021-07-14 17:23:28 -05:00
Ross Thompson
adce800041
Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled.
2021-07-14 15:47:38 -05:00
Ross Thompson
f4295ff097
Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
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This solves the committedM issue.
2021-07-14 15:00:33 -05:00
Ross Thompson
9b756d6a94
Implemented uncached reads.
2021-07-13 23:03:09 -05:00
Ross Thompson
e8bf502bc2
Added CommitedM to data cache output.
2021-07-13 22:43:42 -05:00
Ross Thompson
3e57c899a2
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Ross Thompson
baa2b5d15f
Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
2021-07-13 14:51:42 -05:00
Ross Thompson
3c1a717399
Fixed the fetch buffer accidental overwrite on eviction.
2021-07-13 14:21:29 -05:00
Ross Thompson
32f27cfecf
Dcache AHB address generation was wrong. Needed to zero the offset.
2021-07-13 14:19:04 -05:00
