Ross Thompson 3f780f012a Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. ... Also forgot to include cacheLRU.sv file.		2021-07-20 23:17:42 -05:00
..
cache-sram.sv	A few more cache fixes	2021-04-13 01:07:40 -04:00
cacheLRU.sv	Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux.	2021-07-20 23:17:42 -05:00
dcache.sv	Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux.	2021-07-20 23:17:42 -05:00
DCacheMem.sv	Progress towards the test bench flush.	2021-07-12 14:22:13 -05:00
dmapped.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
icache.sv	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
ICacheCntrl.sv	Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.	2021-07-09 15:16:38 -05:00
ICacheMem.sv	Partial implementation of the data cache. Missing the fsm.	2021-07-07 17:52:16 -05:00
sram1rw.sv	change sram1rw to have a small delay so that we don't have signals changing on clock edges	2021-07-19 11:30:07 -04:00