bbracker
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6e460c5032
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replace physical address checking with virtual address checking because address translator is broken
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2021-07-21 19:47:13 -04:00 |
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bbracker
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f9b6bd91f5
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fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk
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2021-07-20 17:55:44 -04:00 |
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bbracker
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a3823ce3a9
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commented out old hack that used hardcoded addresses
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2021-07-20 15:03:55 -04:00 |
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bbracker
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6b72b1f859
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ignore mhpmcounters because QEMU doesn't implement them
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2021-07-20 13:37:52 -04:00 |
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bbracker
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9e658466e6
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testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
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2021-07-20 05:40:39 -04:00 |
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bbracker
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3b10ea9785
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major fixes to CSR checking
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2021-07-20 00:22:07 -04:00 |
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bbracker
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c1d63fe77c
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MemRWM shouldn't factor into PCD checking
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2021-07-19 18:03:30 -04:00 |
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bbracker
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f7d040af1e
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make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
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2021-07-19 17:11:42 -04:00 |
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bbracker
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65df5c087b
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adapt testbench to removal of ReadDataWEn signal
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2021-07-19 15:42:14 -04:00 |
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bbracker
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ae5663a244
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adapt testbench to removal of signal
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2021-07-19 15:41:50 -04:00 |
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bbracker
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cd469035be
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make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
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2021-07-19 15:13:03 -04:00 |
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bbracker
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5e9dcb3f1c
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linux testbench progress
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2021-07-18 18:47:40 -04:00 |
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bbracker
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82fc766819
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swapped out linux testbench signal names
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2021-07-17 14:48:12 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Ben Bracker
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59b177beac
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stop busybear from hanging
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2021-07-02 17:22:09 -05:00 |
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bbracker
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13cf7c0934
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linux testbench now ignores HWRITE glitches caused by flush glitches
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2021-06-25 09:28:52 -04:00 |
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bbracker
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5b47da21ba
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made testbench-linux's PCDwrong be FlushD
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2021-06-25 08:15:19 -04:00 |
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bbracker
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be962cb1ff
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overhauled linux testbench and spoofed MTTIME interrupt
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2021-06-24 01:42:35 -04:00 |
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David Harris
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1ec90a5e1f
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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bbracker
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3000c27acd
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linux actually uses FPU now!
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2021-06-20 22:29:21 -04:00 |
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bbracker
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2643130c41
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read from MSTATUS workaround because QEMU has incorrect MSTATUS
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2021-06-20 10:11:39 -04:00 |
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bbracker
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14ae87ff0a
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testbench update b/c QEMU extends 32b CSRs to 64b
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2021-06-20 09:24:19 -04:00 |
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bbracker
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c77aabdc6f
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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918ff5093a
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MSTATUS workaround
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2021-06-20 04:48:09 -04:00 |
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bbracker
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069a79fafd
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workaround for ignoring MTIME
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2021-06-20 02:26:39 -04:00 |
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bbracker
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d62d9a7aac
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make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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bbracker
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8d242d73b5
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fixed PCtext error by using blocking assignments
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2021-06-18 17:37:40 -04:00 |
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bbracker
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03a45aeef1
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restore graphical buildroot sim
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2021-06-18 11:58:16 -04:00 |
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David Harris
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336936cc39
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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5b96f7fbd7
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making linux waveforms more useful
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2021-06-17 08:37:37 -04:00 |
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bbracker
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b459d0cc80
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changed parsedCSRs2] to parsedCSRs
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2021-06-17 05:18:14 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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