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Author SHA1 Message Date
David Harris
247f247ad3 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
14b9b8126e rearranging testgen 2021-10-29 22:28:37 -07:00
David Harris
7df4b0c8e7 commented out some failing FPU tests 2021-10-27 11:27:34 -07:00
David Harris
5ceb778914 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-27 11:03:00 -07:00
David Harris
582c2bf37b Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
davidharrishmc
33b8d31c39 Added instructions for making rv32if device 2021-10-27 10:41:37 -07:00
David Harris
589bee5875 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-27 10:37:46 -07:00
David Harris
5783e47e1a Changes for floating point sims 2021-10-27 10:37:35 -07:00
Ross Thompson
7627e177df Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-27 09:59:55 -05:00
Ross Thompson
c4170ece27 Replaced async reset flip flops with sync reset flip flops in cache and bpread. 2021-10-27 09:57:11 -05:00
bbracker
c457fc6e27 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-26 12:43:48 -07:00
bbracker
1591a40f68 bugfix argument passing to GDB script; remove outdated GDB script 2021-10-26 12:43:42 -07:00
David Harris
b7b6d6f23f removed unused signal from wave.do 2021-10-26 09:02:22 -07:00
David Harris
90cf37b881 commented out nonworking tests 2021-10-26 08:56:49 -07:00
David Harris
67adc1d7d5 removed referenc outputs 2021-10-26 08:51:49 -07:00
David Harris
426a43f77b Forgot to save cacheway merge 2021-10-26 08:38:13 -07:00
David Harris
c0145c0a35 merging changes 2021-10-26 08:34:36 -07:00
David Harris
8287a1ef3e Synchronous reset in non-flop blocks 2021-10-26 08:30:35 -07:00
Ross Thompson
c43b19120f Fixed another critical path in the caches. 2021-10-25 22:05:11 -05:00
Ross Thompson
1228dbbebc Fixed the timing issue in the cache replacement polcy. 2021-10-25 18:00:23 -05:00
Ross Thompson
576383c74b Fixed bug with the changes to sram1rw. 2021-10-25 16:11:41 -05:00
Ross Thompson
f0beb4357a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-25 15:36:21 -05:00
Ross Thompson
5fd3f7f2c7 Possible fix for critical path timing in caches. 2021-10-25 15:33:33 -05:00
bbracker
66e53929ce adapt testbench linux to use reset_ext 2021-10-25 13:26:44 -07:00
bbracker
787b54dffc copy / link to checkpoint 8500000 dir 2021-10-25 13:24:02 -07:00
bbracker
39efadf2cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
bbracker
8c4e6baf48 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
David Harris
fbee4963da Converted flops to synchronous reset now that reset signal is synchronized 2021-10-25 11:49:20 -07:00
David Harris
2bf51362e2 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
9b98a499d7 some linux testbench cleanup 2021-10-25 10:04:30 -07:00
Ross Thompson
110d9d3a15 Fixed synthesize script to find the flops after moving. 2021-10-25 09:43:07 -05:00
Ross Thompson
76bba541a7 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. 2021-10-24 21:21:49 -05:00
bbracker
9fdfc750eb checkpoint initialization bugfix 2021-10-24 18:39:51 -07:00
bbracker
13763b002a switch linux graphical sim over to Ross's waves 2021-10-24 18:39:23 -07:00
bbracker
fef09e9a5b remove unused scripts 2021-10-24 15:19:03 -07:00
bbracker
09959617c6 update debugger script to new style 2021-10-24 15:18:44 -07:00
bbracker
cc484569cd fix typo 2021-10-24 15:05:00 -07:00
bbracker
046a78a8fc manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
bbracker
3531a934c9 checkpoint generator bugfix 2021-10-24 14:46:56 -07:00
Ross Thompson
8a51fe76c1 Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
bbracker
c0a7b12f94 or actually needed to reduce expectations of buildroot 2021-10-24 06:59:34 -07:00
bbracker
d3969bb1ba increase regression's expectations of buildroot 2021-10-24 06:50:22 -07:00
bbracker
36b39358c6 add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
bbracker
d445095f1b revamp linux testvector generation for refactoring checkpoint generation 2021-10-24 06:14:11 -07:00
bbracker
e0b6566cbd buildroot do scripts now compile flops 2021-10-23 23:14:59 -07:00
bbracker
26eead1c77 add W stage signals to linux testbench 2021-10-23 14:00:53 -07:00
bbracker
de6a52f6eb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
3c0b0987d2 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
200eb453fb wrapping up lint cleanup; many unused signals removed 2021-10-23 12:15:14 -07:00
David Harris
c9e9cd4a60 more lsu/ifu lint cleanup 2021-10-23 12:10:13 -07:00