forked from Github_Repos/cvw
		
	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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						5ceb778914
					
				@ -14,6 +14,8 @@ cd ../addins
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git clone https://github.com/riscv-non-isa/riscv-arch-test
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git clone https://github.com/riscv-software-src/riscv-isa-sim
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cd riscv-isa-sim
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cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
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<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
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mkdir build
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cd build
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set RISCV=/cad/riscv/gcc/bin   (or whatever your path is)
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