Xavi/cvw
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296 Commits

Author SHA1 Message Date
Ross Thompson
66e9380cfb Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
Kip Macsai-Goren
d031c003ba fixed arch bge test signature output location after update 2022-03-29 20:45:18 +00:00
Kip Macsai-Goren
a6d90a25c2 fixed signature location of the new periph with no compressed instructions 2022-03-29 02:15:17 +00:00
Skylar Litz
f91fb7a388 add AtemptedInstructionCount signal 2022-03-26 21:28:57 +00:00
Kip Macsai-Goren
7ae1d14191 added basic trap tests that do not pass regression yet. updated signature adresses 2022-03-25 22:57:41 +00:00
bbracker
6f6663cd67 fix multiple-context PLIC checkpoint generation 2022-03-25 01:02:22 +00:00
bbracker
d33de3ef6b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
4b376e2834 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
71aad2d213 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
aa60b57fb3 Cleanup in testbench-linux.sv. 2022-03-22 22:34:38 -05:00
Ross Thompson
b2487f4b72 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Ross Thompson
4ca9458534 added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP. 2022-03-22 21:28:34 -05:00
Ross Thompson
e6b42cb10f Added spoof of uart addresses +0x2 and +0x6. 2022-03-22 16:52:27 -05:00
Katherine Parry
e3d01c875b FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
7a25d577ba Added new asserts to testbench. 2022-03-11 15:41:53 -06:00
bbracker
742e8d98cd fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
92e1583db5 change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
David Harris
e4d18f1808 removed more old 64priv tests 2022-03-04 03:57:19 +00:00
bbracker
c3e59ae2df comment out nonfunctioning CSR-PERMISSIONS-M test 2022-03-04 00:11:55 +00:00
bbracker
79ff8d3c80 remove imperas32p tests 2022-03-04 00:06:18 +00:00
bbracker
87aad1d953 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00
bbracker
4fe35aadf2 add rv32a tests to regression 2022-03-02 17:54:55 +00:00
bbracker
b6031bb15f fix buildroot checkpointing and add it back to regression 2022-03-02 16:00:19 +00:00
bbracker
29179c6787 add LRSC test and add wally64a to regression 2022-03-02 07:09:37 +00:00
bbracker
a8e8cfb838 switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv 2022-03-01 03:11:43 +00:00
bbracker
d8ddda760b deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test 2022-03-01 00:37:46 +00:00
David Harris
329fea9329 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
bbracker
ac114e1c6d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
202bd2f8f8 change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests 2022-02-22 03:46:08 +00:00
Kip Macsai-Goren
04892c5d38 added scratch register tests for 64 and 32 bits 2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
324efa7d42 added 32 bit pma tests to regression even though they've been working fo a while 2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
dcb5d0f6a9 Added misa test for both 32 and 64 bits 2022-02-18 19:41:50 +00:00
Kip Macsai-Goren
e16581d73d added CSR permission and minfor to 32 bit tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
943c4d9d7c merged test macros in with 32 bit tests 2022-02-15 20:19:14 +00:00
David Harris
f734afb866 Just needed to recompile - all good. Now removed uretM because N-mode is depricated 2022-02-15 19:48:49 +00:00
Kip Macsai-Goren
9ff4025844 light cleanup for privileged tests 2022-02-15 17:06:16 +00:00
David Harris
64e9f4c0d3 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00
David Harris
f00b3ac27e Fixed TIM tests; rv32e test still failing 2022-02-08 15:24:37 +00:00
David Harris
76dccbad91 Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail 2022-02-08 12:40:02 +00:00
David Harris
c61cd55c5c Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
David Harris
cbef88ec10 Lab 3 file cleanup 2022-02-08 10:26:37 +00:00
Kip Macsai-Goren
0eb280b314 added new tests to make and testbench 2022-02-06 19:47:22 +00:00
bbracker
f67af23bf3 remove sporadic tabs from tests.vh so that it is now only spaces 2022-02-05 23:07:38 +00:00
David Harris
72bc64ef28 Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
David Harris
2c67f32b97 RV32e tests 2022-02-04 14:30:36 +00:00
David Harris
a6708ed887 cache cleanup 2022-02-03 15:36:11 +00:00
David Harris
38bbe23d14 More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
David Harris
da8819d64b changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
David Harris
02071700d6 Removed Busybear dependencies 2022-02-02 20:28:21 +00:00
Ross Thompson
f4a553fd7d Fixed testbench so coremark stops. 2022-02-02 11:37:48 -06:00
Ross Thompson
4b4cee3ddd Added correct stop condition for coremark. 2022-02-02 09:53:51 -06:00
Ross Thompson
143bdaa288 Modified makefiles to generate function address to name mappings for modelsim. 2022-02-01 18:25:03 -06:00
Ross Thompson
f055441ecf Improved function_radix to not printout warnings when no valid function is found. 2022-02-01 18:03:09 -06:00
Ross Thompson
5407b72af9 Setup the main regression test to be able to handle coremark. 2022-02-01 17:00:11 -06:00
Ross Thompson
86bac2a083 partial ifu cleanup. 2022-01-31 16:08:53 -06:00
Ross Thompson
5ce8dd60c5 Fixed modelsim warning with linux simulation. 2022-01-31 12:57:02 -06:00
Ross Thompson
c2b2fae98d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-31 12:17:37 -06:00
Ross Thompson
9cd502d0af Encapsulated dtim. 2022-01-31 11:23:55 -06:00
Kip Macsai-Goren
242b27705d added machine info test that uses new test library 2022-01-31 05:54:43 +00:00
David Harris
090533cfe9 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
David Harris
7f91170bab Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
David Harris
21bdce63ff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
David Harris
07425369fc Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
David Harris
b63e53bbdb Defined rv32e and rv32emc configs 2022-01-17 14:01:01 +00:00
David Harris
6febce0001 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00
David Harris
2bf4676ff8 LSU cleanup 2022-01-14 23:55:27 +00:00
David Harris
43abf25417 moved fp to tests 2022-01-14 23:05:59 +00:00
David Harris
ae6792e354 Moved fp tests from testbench to tests/fp 2022-01-14 23:00:46 +00:00
Ross Thompson
3bec276862 Added tim only test to regression-wally. Minor cleanup to ifu. 2022-01-14 11:13:06 -06:00
James E. Stine
e0e30c1e9e Update to TestFloat for scripts so can run automatically once 
TestFloat/Softfloat is compiled.  Slight change to the README as well.
 2022-01-14 09:25:37 -06:00
Ross Thompson
a973681a90 Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon. 2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7 Partial local dtim in lsu configuration. 2022-01-13 17:50:31 -06:00
Kip Macsai-Goren
c251144460 Fixed PMA regions, Added passing PMA tests to regression 2022-01-10 22:08:26 +00:00
David Harris
3a2b459439 Merged coremark changes 2022-01-10 05:09:28 +00:00
David Harris
39d5570d2c Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark. 2022-01-10 05:04:13 +00:00
Ross Thompson
ae927e2bc6 Fixed wavefile. 
Converted coremark to use elf2hex.
 2022-01-09 22:03:10 -06:00
David Harris
bea6d0856d Testbench directory cleanup 2022-01-07 17:02:16 +00:00
David Harris
120fb7863f Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
David Harris
1d8451c2cf Capitalized LSU and IFU, changed MulDiv to MDU 2022-01-07 04:30:00 +00:00
David Harris
08231d4e66 Tests cleanup: 2022-01-06 23:07:22 +00:00
Katherine Parry
b3ebce0365 some FPU test fixes 2022-01-06 23:03:20 +00:00
David Harris
1c96b22b8f More FP unpacking fix 2022-01-06 22:22:22 +00:00
David Harris
2b8e8707a7 Floating point test cleanup 2022-01-06 21:45:16 +00:00
David Harris
55e757db03 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 18:10:32 +00:00
David Harris
c9aa21d5a3 FPU debug and configurable logic cleanup 2022-01-06 18:10:25 +00:00
Ross Thompson
77efcad15b Changed names of address in caches. 
Removed old cache files.
 2022-01-05 22:19:36 -06:00
David Harris
e33db012ba Reinstated many arch f/d tests that had failed because of memfile issues 2022-01-05 22:44:10 +00:00
David Harris
31067c8e7d Restored many of the arch32f and arch64d that had been failing because of memfile issues 2022-01-05 22:23:46 +00:00
David Harris
85fa620cfb Finished removing generate statements 2022-01-05 16:41:17 +00:00
David Harris
32590d484c Removed more generate statements 2022-01-05 16:25:08 +00:00
Ross Thompson
06168e67e4 Switched block for line in caches. 2022-01-04 22:08:18 -06:00
David Harris
08e6a10480 Removed imperas mmu tests; using wallypriv instead 2022-01-04 23:14:53 +00:00
Kip Macsai-Goren
87ba45ce36 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 21:30:51 +00:00
Kip Macsai-Goren
0ee4e03cd6 fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh. 2022-01-04 21:30:38 +00:00
David Harris
57daff45c8 Fixed bad address for F/fmsub_b18-01 2022-01-04 21:04:06 +00:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00