Ross Thompson
7497422667
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Ross Thompson
32f0b97cd3
Updated uncore to use sdc.
...
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
Ross Thompson
77e2b6f9a9
Merge branch 'main' into fpga
2021-10-22 16:09:16 -05:00
Katherine Parry
7c7c0f538a
put the FMA priority encoders into their own module
2021-10-22 10:03:12 -07:00
Ross Thompson
de4ea16d32
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
David Harris
47e19d4caa
moved coemark and testsBP to tests
2021-10-20 09:10:06 -07:00
Ross Thompson
d11136c406
Fixed bug with the external memory region selection.
...
Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
David Harris
00d8035836
Fixed multiplier and pointed arch tests to new path in addins
2021-10-18 15:43:59 -07:00
James E. Stine
c5b99300e7
Clean up some signals - beautification onging
2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
869c35ba1c
Fixed typo in imperas64mmu tests causing PMP tests not to run.
2021-10-14 13:42:24 -07:00
James E. Stine
1dba57dce7
Update to fpdivsqrt to go on posedge as it should. Also an update to
...
individual regression test for TestFloat (still needs some tweaking)
2021-10-13 17:14:42 -05:00
bbracker
4abc6fc915
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
Ross Thompson
f6c6cb9ed2
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
Ross Thompson
bfe633d087
Partially working sd card reader.
2021-10-11 10:23:45 -05:00
David Harris
75c17dc372
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
James E. Stine
2b66615812
Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH
2021-10-10 15:44:01 -05:00
bbracker
a88ae5aaff
use correct string formatting function
2021-10-10 10:09:59 -07:00
bbracker
6fce53d146
make testbench-linux halt on some discrepancies with QEMUw
2021-10-09 17:22:30 -07:00
Kip Macsai-Goren
303beaa083
updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully.
2021-10-08 15:40:18 -07:00
David Harris
3d0383c154
moved fp vectors into vectors subdirectory
2021-10-07 23:28:06 -04:00
David Harris
6dd85b80a2
Included TestFloat and SoftFloat
2021-10-07 23:03:45 -04:00
James E. Stine
28e147bb19
update scripts
2021-10-07 15:14:54 -05:00
James E. Stine
8429078d4f
TV for conversion and compare
2021-10-06 14:38:32 -05:00
James E. Stine
93668b5185
Update to testbench for FP stuff
2021-10-06 13:16:38 -05:00
James E. Stine
2afa6e7a6e
Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included
2021-10-06 08:56:01 -05:00
Skylar Litz
5bcae393c9
added delayed MIP signal
2021-10-04 18:23:31 -04:00
Ross Thompson
8653a87e24
Added more debug flags.
2021-10-03 11:41:21 -05:00
David Harris
48e33c79a9
Reduced cycle count for DIVW/DIVUW by two
2021-10-03 09:42:22 -04:00
David Harris
2ae51d1852
Parameterized number of bits per cycle for integer division
2021-10-03 01:10:15 -04:00
David Harris
fbe6e41169
Divide performs 2 steps per cycle
2021-10-02 09:19:25 -04:00
David Harris
e11c565a6f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 23:15:34 -04:00
bbracker
6aa79657ed
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit fec96218f6
2021-09-30 20:45:26 -04:00
David Harris
caa36f267d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 20:07:43 -04:00
Ross Thompson
fca9b9e593
Movied tristate to test bench level.
2021-09-30 11:27:42 -05:00
Ross Thompson
cefbcd1b0c
Partially sd card read on fpga.
2021-09-30 11:23:09 -05:00
David Harris
42d573be57
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
bbracker
fec96218f6
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
Ross Thompson
7ca801113e
Added debugging directives to system verilog.
2021-09-27 13:57:46 -05:00
bbracker
7117c0493c
condense testbench code; debug_level of 0 means don't check at all
2021-09-27 03:03:11 -04:00
Ross Thompson
7d749b201b
added support to due partial fpga simulation.
2021-09-26 15:00:00 -05:00
Ross Thompson
4d1b02c068
Merge branch 'main' into fpga
2021-09-26 13:22:53 -05:00
Ross Thompson
c917f14b6b
Almost done writting driver for flash card reader.
2021-09-25 19:05:07 -05:00
Ross Thompson
69674f272a
We now have a rough sdc read routine.
2021-09-25 17:51:38 -05:00
Ross Thompson
44196af61a
Have program which checks for sdc init and issues read, but read done is
...
not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Ross Thompson
4f7bc1be48
Added either the sdModel or constant driver for the SDC ports in all test benches.
2021-09-24 12:31:51 -05:00
Ross Thompson
9fdb1d3cc9
setup so the sdc does not need to load a model in the imperas test bench.
2021-09-24 11:30:52 -05:00
Ross Thompson
c644e940c2
Updated Imperas test bench to work with the SDC reader.
2021-09-24 11:22:54 -05:00
bbracker
3f96ff0ac0
switch testbench-linux's interrupts from xcause to mip and improve warning messages
2021-09-22 12:33:11 -04:00
bbracker
ff5379fd95
fix regression
2021-09-15 17:30:59 -04:00
David Harris
92385a1d51
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-13 12:41:07 -04:00
