29 Commits

Author	SHA1	Message	Date
David Harris	865d5ce0b1	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
Kevin	98420cb988	dot stars conversions on the rest of the testbenches	2021-12-12 17:53:26 -08:00
Kevin	1a82b50483	edited one testbench, yet to run regression	2021-12-10 20:26:20 -08:00
Ross Thompson	9ddd065340	Updated coremark testbench with the extra ports from FPGA merge. ... Fixed coremark Makefile to create work directory.	2021-12-08 13:40:32 -06:00
Ross Thompson	5642918ead	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
David Harris	82cfebfb83	Coremark Cleanup, trying compile from addins	2021-11-19 06:09:04 -08:00
David Harris	690410721d	Cleaning up CoreMark benchmark	2021-11-18 20:12:52 -08:00
David Harris	8e8b84f532	vert "Simplifying riscv-coremark" ... This reverts commit ce8232e396.	2021-11-18 18:40:13 -08:00
David Harris	ce8232e396	Simplifying riscv-coremark	2021-11-18 17:15:40 -08:00
David Harris	402b473dbb	CoreMark testing	2021-11-18 16:14:25 -08:00
Ross Thompson	4f7bc1be48	Added either the sdModel or constant driver for the SDC ports in all test benches.	2021-09-24 12:31:51 -05:00
Ross Thompson	74fba4bb06	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
David Harris	1ec90a5e1f	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
Elizabeth Hedenberg	2d1d929485	coremark print statment	2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg	2a33673e3c	coremark updates	2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg	463ba1a2be	coremark directory changes	2021-05-03 19:35:06 -04:00
Thomas Fleming	3c49fd08f6	Remove imem from testbenches	2021-04-14 20:20:34 -04:00
ushakya22	6b9ae41302	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
Teo Ene	a3aa103dc7	Fix typo from last commit	2021-03-24 17:09:58 -05:00
Teo Ene	e43849b82c	Updated coremark_bare testbench for IM	2021-03-24 17:04:43 -05:00
Shreya Sanghai	09faa40eb6	fixed minor bugs in testbench	2021-03-18 17:37:10 -04:00
Teo Ene	57f1ca5259	Switched coremark to RV64IM	2021-03-17 22:39:56 -05:00
Teo Ene	d2fe42d6d0	adapted coremark bare testbench to new dtim RAM HDL	2021-03-17 16:59:02 -05:00
Teo Ene	4fd0ecff69	Temporarily reverted my last few commits	2021-03-17 15:16:01 -05:00
Teo Ene	3e849f99a6	fix to last commit	2021-03-17 15:02:15 -05:00
Teo Ene	dfe6df2e00	Added Ross's addr lab stuff to coremark stuff	2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg	041439c008	fixing coremark branch prediction	2021-03-17 15:15:55 -04:00
Teo Ene	06be82fc67	Added stop to coremark_bare testbench	2021-03-04 07:47:07 -06:00
Teo Ene	396dc61564	Linux CoreMark and baremetal CoreMark split into two separate tests/configs	2021-03-04 07:44:33 -06:00